Bandi Venkata Chandan

About

I, Bandi Venkata Chandan, was born in Visakhapatnam, India, in 1995. In 2016, I obtained a B.Tech. degree in Electronics and Communication Engineering from the Indian Institute of Information Technology, Design and Manufacturing (PDPM-IIITDM), located in Jabalpur, India. I obtained a First Class Distinction in my M. Tech. degree from the School of Nanotechnology at Jawaharlal Nehru Technological University Kakinada (JNTUK) in 2022, India. Furthermore, I successfully qualified for the GATE examination in 2019 and was awarded a merit scholarship by the Government of India for my master's studies from 2019 to 2022.


My research area focuses on the Modeling & Simulations of Micro and Nano Semiconductor Devices, the Design of Nano Device Sensors for Bio-medical Applications, and Linearity & High-Frequency analysis of Hetero-Material Devices.

Employment

• Industrial Training Institute, Visakhapatnam Teaching Assistant
  2020 - 2022
• Indian Institute of Information Technology Design and Manufacturing Jabalpur Research Fellowship
  2017 - 2019

Education

• Indian Institute of Information Technology Design and Manufacturing Jabalpur Bachelor of Technology
  2012 - 2016

Projects & Funding

Projects & funding information is unavailable.

Publications (24)

• Design and Reliability Assessment of a Reconfigurable Tunneling Device for Ultra Low-Power Applications
  IEEE Transactions on Device and Materials Reliability 2026 DOI: 10.1109/TDMR.2026.3708312
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• A Dielectric-Modulated Dual-Material-Gate MOS-HEMT for Ultrahigh Sensitivity Label-Free Biosensor
  IEEE Transactions on Dielectrics and Electrical Insulation 2026 DOI: 10.1109/TDEI.2026.3698812
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• Insights Into the Effects of Interface Trap Charges on Electrostatic-Based Magnesium Silicide Tunneling Interface
  IEEE Transactions on Device and Materials Reliability 2025 DOI: 10.1109/TDMR.2025.3621826
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• Theoretical performance and reliability optimization of graphene based electrically doped tunnel FET under interface trap charge constraints: A device-level approach
  Microelectronics Reliability 2025 DOI: 10.1016/j.microrel.2025.115928
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• Impact of interface trap densities on Mg2Si-based electrostatically doped tunnel FET
  Modelling and Simulation in Materials Science and Engineering 2025 DOI: 10.1088/1361-651X/ae0daa
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• Numerical analysis and parametric optimization of multi-absorber layer all-inorganic perovskite solar cells employing double perovskites
  Modelling and Simulation in Materials Science and Engineering 2025 DOI: 10.1088/1361-651X/ae0b9b
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• Modelling and Simulation of Heterojunction TFETs: Tackling Performance Challenges Through Machine Learning and Advanced Computational Techniques
  2024 DOI: 10.1145/3745812.3745860
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• Theoretical and simulation-based assessment of electrically doped junctionless TFET with metal-strip and hetero-material considering interface trap charges
  Microelectronics Reliability 2024 DOI: 10.1016/j.microrel.2024.115393
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• Performance and Analysis of Stack Junctionless Tunnel Field Effect Transistor
  Silicon 2022 DOI: 10.1007/s12633-021-00958-z
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• Influence of Nano Ranged Stack Gate on Junctionless Tunnel Field Effect Transistor
  2021 7th International Conference on Signal Processing and Communication (ICSC) 2021 DOI: 10.1109/icsc53193.2021.9673223
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