Dr. Saroja V Siddamal

Employment

• KLE Technological University Professor

Education

Education history is unavailable.

Projects & Funding

Projects & funding information is unavailable.

Publications (28)

• Design and Implementation of 16-Bit Posit Arithmetic
  2024 DOI: 10.1007/978-981-97-4657-6_4
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• Out-of-Order Execution of Instructions for In-Order Five-Stage RISC-V Processor
  2024 DOI: 10.1007/978-981-97-0767-6_3
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• Prefetching Mechanism for Distributed Cache Architecture: Trends and Challenges
  2024 DOI: 10.1007/978-981-97-7710-5_7
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• 2×VDD IO buffer with 1×VDD devices considering hot-carrier and gate-oxide reliability issues
  Integration 2024 DOI: 10.1016/j.vlsi.2024.102230
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• A Survey on In-Order 5-Stage Pipeline RISC-V Processor Implementation
  2023 DOI: 10.1007/978-981-19-0098-3_73
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• Design and Verification of Five-Stage Pipelined Architecture Using SV-Verification Methodology Module
  2023 DOI: 10.1007/978-981-99-5652-4_34
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• Hardware Architecture of Reinforcement Learning for Edge Devices
  2023 DOI: 10.1007/978-981-99-4932-8_15
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• Differential receiver with 2 × VDD input signals using 1 × VDD devices
  Integration 2022 DOI: 10.1016/j.vlsi.2022.08.003
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• Mixed-Voltage I/O Buffer Using NMOS Blocking Considering Gate Oxide Reliability
  Journal of Circuits, Systems and Computers 2022 DOI: 10.1142/S0218126622502024
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• Implementation of 32-bit ISA Five-Stage Pipeline RISC-V Processor Core
  2022 DOI: 10.1007/978-981-19-1653-3_19
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