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Publications (5)
- Design and analysis of gate underlapped GOI junctionless FinFET in presence of temperature variations for RF IC design applications Save
- Device and circuit level performance assessments of gate engineered Ge/GaAs heterojunction doping less TFET Save
- Investigation of Device and Circuit-Level Performances of Dielectric Engineered Dopingless SOI Schottky Barrier MOSFET Save
- Performance Assessments of Gate Engineered Dopingless Schottky Tunnel MOSFET in Presence of Interfacial Trap Charges Save
- Performance Enhancement of Dielectric Engineered Doping Less InGaN Tunnel FET for Low Power Analog/Radio Frequency Applications Save