DS
Deepesh Sharma
Indian Institute of Technology Delhi, National Institute of Technology Srinagar
0000-0002-9861-710X
Employment
Employment history is unavailable.
Education
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Indian Institute of Technology Delhi PhD2021 - 2026
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National Institute of Technology Srinagar Btech2017 - 2021
Projects & Funding
Projects & funding information is unavailable.
Publications (10)
- Impact of Back-Bias on Analog Performance at Cryogenic Temperature in 22-nm FDSOI MOSFETs for Quantum Computing Applications Save
- A Unified Compact Model for Full-CMOS-Based Hybrid SET–FET Circuits Save
- Cryogenic Performance and Modeling of Sub-5nm Fin-Width Bulk FinFETs for Quantum Computing Applications Save
- Investigation and Subcircuit Modeling of Self-Heating in PDSOI NFETs at Cryogenic Temperatures Using Pulsed I – V Technique for Co-Integrated Quantum Technologies Save
- Cryogenic Compact Modeling for Sub-5nm Fin Width Bulk FinFETs for Quantum Computing Applications Save
- Impact of Co-Integration on the Performance of Full CMOS Based Hybrid SET-FET Circuits for Scalable Quantum Computing using FinFET Technologies Save
- Memory effects in 45-nm PDSOI MOSFETs at Cryogenic Temperatures for Quantum Computing Applications Save
- Multiple-Gate FET Quantum Dot Behavior and a Proximity Charge Sensing Model Save
- Quantum-Dot-Based Thermometry Using 12-nm FinFET and Machine Learning Models Save
- Compact Model of a Bulk FinFET Quantum Dot Toward Single Chip Integration of Qubits and Control Electronics for Quantum Computing Applications Save