Vishesh Dokania

Employment

• Intel Corporation Design Engineering Intern
  2016 - Present

Education

• University of California, Los Angeles Master of Science
  2015 - Present
• Birla Institute of Technology Bachelor of Engineering
  2011 - 2015

Projects & Funding

Projects & funding information is unavailable.

Publications (3)

• Analytical Modeling of Wrap-Gate Carbon Nanotube FET With Parasitic Capacitances and Density of States
  IEEE Transactions on Electron Devices 2016 DOI: 10.1109/TED.2016.2581119
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• Circuit-level design technique to mitigate impact of process, voltage and temperature variations in complementary metal-oxide semiconductor full adder cells
  IET Circuits, Devices & Systems 2015 DOI: 10.1049/iet-cds.2014.0167
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• Design of variation-resilient CNFET-based Schmitt trigger circuits with optimum hysteresis at 16-nm technology node
  2013 Annual IEEE India Conference (INDICON) 2013 DOI: 10.1109/indcon.2013.6725885
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