Dr G Mamatha
JNTUA, Jawaharlal Nehru Technological University Anantapur College of Engineering Ananthapuramu
0000-0003-0279-7554
About
Professional Summary
Expert in VLSI and Embedded Systems working as Assistant Professor at Jawaharlal Nehru Technological university Anantapur College of Engineering Anathapuramu. IEEE Senior Member with more than 15 years of experience in Teaching and Research Distinguished record of publication in academic journals all over the world. Out of passion towards research submitted several research proposals for funding agencies. Research Project titled "Implementation of loT Security Solutions for Health Care Monitoring Systems” was sanctioned by the Science and Engineering Research Board (SERB) Government of India with cost of Rs. 21, 25,520/- (Rs. Twenty One Lakh Twenty Five Thousand Five Hundred and Twenty Only).
As a technical mentor the project named design and development of System on Chip (SoC) named "ANANTH" is developing in collaboration with the OpenPOWER foundation and International Business Machines (IBM) Inc., ANANTH is a soft IP-based fabless SoC, developing on the Power ISA which is the most sophisticated open source processor architectures available in the OpenPOWER Foundation. The Power ISA is an instruction set architecture (ISA) currently developed by the OpenPOWER Foundation, led by IBM. Always open development drives hundreds of innovations across VLSI, IOT, artificial intelligence, supercomputing, hyperscale and more. This fabless SoC is being built from the ground up to meet the needs of IoT and academic R&D workloads and applications.
ANANTH SoC built around IBM POWER A2I CORE comes with peripherals like AMBA AXI core, SPI, I2C, ETHERNET, PCIe, NAND & NOR/ Controller , DDR3 memory controller, DMA engine. This project is being designed and developed with Mentor Graphics® tool chain, one of the EDA tool ease the designing of integrated circuits on a large scale, JNTUACEA department of ECE has this technological leader in electronic design automation for software and hardware design solutions. IBM Power Systems Academic initiative program Manager itself recognised the mentorship towards research project.
Education:
Ph.D, Electronics and communications Engineering, “Implementation of High Speed Dwt Based Satellite Image Fusion Algorithms on Re-Configurable Hardware", JNTU University, Anantapuramu in 2015
M.Tech., Digital Systems and Computer Engineering, JNTU University Hyderabad ,2006,
B.Tech., Electronics and Communication Engineering, Nagarjuna University, Guntur, 2000
Employment
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JNTUA Coordinator2021 - 2022
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Jawaharlal Nehru Technological University Anantapur College of Engineering Ananthapuramu Associate Professor HoD2011 - 2033
Education
Education history is unavailable.
Projects & Funding
Projects & funding information is unavailable.
Publications (29)
- Improved Read/Write Stability based Level Shift 5T Ternary SRAM Cell Design using Enhanced Gate Diffusion Input BWGCNTFET Save
- Improved Read/Write Stability-Based Level Shift 5T Ternary SRAM Cell Design using Enhanced Gate Diffusion Input BWGCNTFET, Save
- An efficient 5-Transistor SRAM Cell Design using FNSBS-CNTFET for improving Read and Write Stability Save
- Convert Wireless Communication in IoT Network Using THz Band Save
- DESIGN, DEVELOP, AND INTEGRATION OF DMA CONTROLLER FOR OPEN- POWER BASED PROCESSOR SOC Save
- Design, Development, and Integration of DMA Controller for Open-Power-Based Processor SOC Save
- Implementaion of radar digital receiver using intel integrated performance primitives Save
- Implementation of radar digital receiver using intel integrated performance primitives Save
- Implementation of security algorithm using light weight block cipher in IoT Applications Save
- Implementation of 10TSRAM cell on comparison of power dissipation with 7TSRAM cell Save