Syed Ershad Ahmed

About

Dr. Syed Ershad Ahmed is an Assistant Professor at the Electrical and Electronics Engineering (EEE) Department, BITS Pilani, Hyderabad Campus. He earned his Ph.D. from BITS Pilani in 2018, specializing in high-performance binary, logarithmic, and BCD multipliers. His research focuses on optimizing digital arithmetic circuits for precision, area, delay, and power efficiency.

With expertise in VLSI Arithmetic and Digital Design, Dr. Ahmed has published extensively on approximate multiplier architectures and their applications in media processing and neural networks. He has received several awards, including the IEEE PrimeAsia Gold Leaf Award and international travel grants for presenting his research.

Dr. Ahmed is actively involved in projects on system-on-chip designs and hardware architectures for media processing. He has been with BITS Pilani since 2009, contributing to both teaching and research in microelectronics.

Employment

• Birla Institute of Technology and Science - Hyderabad Campus Assistant Professor
  2009 - 2017

Education

• BITS Pilani, Hyderabad Campus

Projects & Funding

Projects & funding information is unavailable.

Publications (61)

• Energy Efficient Approximate Multiplier for Error Resilient Applications
  Journal of Circuits, Systems and Computers 2026 DOI: 10.1142/S0218126626500854
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• HTAM: High-Performance Ternary Approximate Multiplier Designs With Stage-Wise Optimization for Low PDP and High Accuracy
  IEEE Transactions on Emerging Topics in Computing 2026 DOI: 10.1109/TETC.2026.3687573
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• Exploring Posit Multiplication: A Comprehensive Review of Booth and Logarithmic Mantissa Methods
  IET Computers & Digital Techniques 2026 DOI: 10.1049/cdt2/7515558
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• T-LEAP Posit: A Truncated Logarithmic Enhanced Arithmetic Posit Multiplier for Area–Power Efficient and Accuracy-Robust Deep Neural Networks
  IEEE Access 2026 DOI: 10.1109/ACCESS.2026.3697561
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• Novel Decoder Based Approach for Area Efficient Accurate and Approximate Unsigned Multiplier for FPGA
  Circuits, Systems, and Signal Processing 2026 DOI: 10.1007/s00034-026-03708-x
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• A Power-Efficient Gaussian Filter Architecture Using Adder Compressors for Edge Detection Application
  Circuits, Systems, and Signal Processing 2025 DOI: 10.1007/S00034-024-02894-W
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• Addressing Adversarial Attacks in IoT Using Deep Learning AI Models
  IEEE Access 2025 DOI: 10.1109/ACCESS.2025.3552529
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• Design of Approximate Adder With Reconfigurable Accuracy
  IEEE Access 2025 DOI: 10.1109/ACCESS.2025.3531943
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• Energy-Efficient Decoding and Encoding Hardware for Optimized Posit Arithmetic
  IEEE Embedded Systems Letters 2025 DOI: 10.1109/LES.2024.3485002
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• HEAD: High-Speed Approximate HEterogeneous ADder for Error-Resilient Applications
  Journal of Circuits, Systems and Computers 2024 DOI: 10.1142/S0218126625500070
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