0000-0003-0601-5994 Employment
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Publications (9)
- A Hardware- Efficient Dual- Mode Polynomial Sampling Architecture With Hash Integration For Post-Quantum Cryptography Save
- Low-power Multi-Cauda Comparator Designed Using a Fragmentary Pre-charging Approach Save
- VLSI Architecture of Hardware Accelerator for Transformer AI Model Save
- Low-Complexity lassification Technique and Hardware-Efficient Classify-Unit Architecture for CNN Accelerator Save
- Energy-Efficient and High-Throughput CNN Inference Engine Based on Memory-Sharing and Data-Reusing for Edge Applications Save
- A New Hardware-Efficient VLSI-Architecture of GoogLeNet CNN-Model Based Hardware Accelerator for Edge Computing Applications Save
- An Uninterrupted Processing Technique-Based High-Throughput and Energy-Efficient Hardware Accelerator for Convolutional Neural Networks Save
- A 10-bit 2.33 fJ/conv. SAR-ADC with high speed capacitive DAC switching using a novel effective asynchronous control circuitry Save
- Analysis and Proposal of a Flash Subranging ADC Architecture Save