Mayur Agarwal

Employment

• College of Technology, GBPUAT, Pantnagar Assistant Professor
  2018 - Present

Education

Education history is unavailable.

Projects & Funding

Projects & funding information is unavailable.

Publications (6)

• High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T xor-xnor Cell
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2020 DOI: 10.1109/tvlsi.2020.2983850
  +Save
• High Performance 20-T based Hybrid Full Adder using 90nm CMOS Technology
  2019 Women Institute of Technology Conference on Electrical and Computer Engineering (WITCON ECE) 2019 DOI: 10.1109/witconece48374.2019.9092897
  +Save
• An IEEE Single Precision Floating Point Arithmetic-Based Apodization Architecture for Portable Ultrasound Imaging System
  IEEE Transactions on Circuits and Systems I: Regular Papers 2019 DOI: 10.1109/tcsi.2019.2892459
  +Save
• VLSI architecture for IEEE single precision floating point moving average calculator
  2017 Innovations in Power and Advanced Computing Technologies, i-PACT 2017 2018 DOI: 10.1109/IPACT.2017.8244978
  +Save
• Architecture of a real-time delay calculator for digital beamforming in ultrasound system
  IET Circuits, Devices and Systems 2016 DOI: 10.1049/iet-cds.2015.0189
  +Save
• A new design of low power high speed hybrid CMOS full adder
  2014 International Conference on Signal Processing and Integrated Networks, SPIN 2014 2014
  +Save