Ambika Prasad Shah

About

Ambika Prasad Shah is currently working as an Associate Professor at the Indian Institute of Technology Jammu, India since March 2020. He was the Postdoctoral Fellow at the Institute for Microelectronics, TU Wien from January 2019 to March 2020. He worked for the Ph.D. degree from the Electrical Engineering Department, Indian Institute of Technology Indore, India from July 2016 to December 2018. He received B.E. degree and M.E. degree in Electronics Engineering from Institute of Engineering & Technology, Devi Ahilya University, Indore, India in 2009 and 2015 respectively. Before joining his Ph.D. degree he was Assistant Professor in Electronics & Telecommunication Engineering Department, IET-DAVV, Indore, India from 2010 to 2016. His current research interest includes reliability analysis of digital circuits, reliable SRAM design, low power high-performance digital circuit designs.

Employment

• Indian Institute of Technology Jammu Associate Professor
  2026 - Present
• Indian Institute of Technology Jammu Assistant Professor
  2020 - 2026
• Technische Universität Wien Postdoctoral Fellow
  2019 - 2020
• Devi Ahilya Vishwavidyalaya Assistant Professor
  2010 - 2016

Education

• Indian Institute of Technology Indore Doctor of Philosophy
  2016 - 2019
• Devi Ahilya Vishwavidyalaya Master of Engineering
  2012 - 2015
• Devi Ahilya Vishwavidyalaya Bachelor of Engineering
  2006 - 2009
• Rajiv Gandhi Proudyogiki Vishwavidyalaya Diploma in Engineering
  2003 - 2006

Projects & Funding

Projects & funding information is unavailable.

Publications (57)

• Survey, taxonomy, and methods of QCA-based design techniques-part I: digital circuits
  Semiconductor Science and Technology 2022 DOI: 10.1088/1361-6641/AC5EC0
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• Series diode-connected current mirror based linear and sensitive negative bias temperature instability monitoring circuit
  International Journal of Numerical Modelling: Electronic Networks, Devices and Fields 2022 DOI: 10.1002/JNM.2953
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• Survey, taxonomy, and methods of QCA-based design techniques-part II: reliability and security
  Semiconductor Science and Technology 2022 DOI: 10.1088/1361-6641/AC5EC1
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• Error-Tolerant Reconfigurable VDD 10T SRAM Architecture for IoT Applications
  Electronics 2021 DOI: 10.3390/electronics10141718
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• A Low-Leakage Variation-Aware 10T SRAM Cell for IoT Applications
  Journal of Circuits, Systems and Computers 2021 DOI: 10.1142/S0218126621502431
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• A reliable, multi-bit error tolerant 11T SRAM memory design for wireless sensor nodes
  Analog Integrated Circuits and Signal Processing 2021 DOI: 10.1007/S10470-020-01728-4
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• BTI and Soft-Error Tolerant Voltage Bootstrapped Schmitt Trigger Circuit
  IEEE Transactions on Device and Materials Reliability 2021 DOI: 10.1109/TDMR.2021.3052141
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• D flip-flop based TRNG with zero hardware cost for IoT security applications
  Microelectronics Reliability 2021 DOI: 10.1016/J.MICROREL.2021.114098
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• Design of Fault-Tolerant and Thermally Stable XOR Gate in Quantum dot Cellular Automata
  Th IEEE European Test Symposium (ETS) 2021 DOI: 10.1109/ETS50041.2021.9465459
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• High-performance radiation hardened NMOS only Schmitt Trigger based latch designs
  Analog Integrated Circuits and Signal Processing 2021 DOI: 10.1007/S10470-021-01924-W
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