VP
Vinayak Patil
Centre for Electronics Design and Technology of India, Central Electronics Engineering Research Institute CSIR, University of Pune, College of Engineering, Pune
Employment
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Centre for Electronics Design and Technology of India Director1991 - 1997
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Central Electronics Engineering Research Institute CSIR Scientist1977 - 1991
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Central Water and Power Research Station1976 - 1977
Education
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University of Pune Ph.D? - 1990
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College of Engineering, Pune M.E(E & T/C)? - 1979
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Faculty of Technology & Engineering, Baroda B.E(Electroniics)? - 1975
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Pratap Collge, Amalner B.Sc. (Physics)? - 1972
Projects & Funding
Projects & funding information is unavailable.
Publications (32)
- Impact of multipath delay and co-channel interference on MIMO and STBC-MIMO Save
- Chronological Developments of Wireless Radio Systems Before World War II Save
- Ant Colony Optimization for random network Save
- Computer Network Optimization Using Topology Modification Save
- Historical Perspectives of Development of Antique Analog Telephone Systems Save
- Preparation and characterization of Co 2+ substituted Li–Dy ferrite ceramics Save
- On-line estimation of crystallization parameters and automatic pan feed control Save
- Microprocessor Based Control Strategies and Role of ASICs in Sugar Crystallisation Process Save
- Role of multiple property measurements in the regulation of low-gradesugar strikes. Proceedings Save
- Microprocessor-based vacuum pan monitoring system for sugar crystallization Save