KM
KAVICHARAN MUMMANENI
National Institute Of Technology Silchar, Thapar University, National Institute of Technology Warangal, National Institute of Technology
0000-0003-1074-3564
Employment
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National Institute Of Technology Silchar Assistant Professor2018 - Present
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Thapar University Assistant Professor2017 - Present
Education
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National Institute of Technology Warangal Ph.D2010 - 2015
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National Institute of Technology M.Tech2007 - 2009
Projects & Funding
Projects & funding information is unavailable.
Publications (16)
- Modeling and Analysis of On-Chip Single and H-tree Distributed RLC Interconnects Save
- Modeling and Analysis of On-Chip Single and H-tree Distributed RLC Interconnects Save
- A Survey on FDTD-Based Interconnect Modeling Save
- A survey on FDTD-based interconnect modeling Save
- A Novel Delay and Overshoot Estimation model for VLSI Global Interconnects Save
- An Efficient Distributed Tree Structure Modelling for VLSI circuits Save
- Efficient delay and crosstalk estimation models for current-mode high speed interconnects under ramp input Save
- Efficient delay and crosstalk estimation models for current-mode high speed interconnects under ramp input Save
- Transient analysis of VLSI tree interconnects based on matrix Pade type approximation Save
- A closed-form delay estimation model for current-mode high speed VLSI interconnects Save