Manish Rai

About

DR. MANISH KUMAR RAI
B.Tech from J K Institute of Technology, University of Allahabad. M.Tech and Ph.D from Motilal Nehru National Institute of Technology Allahabad. Research area - Negative Capacitance based Junctionless Nanowire - Modeling and Simulation.

Employment

• Motilal Nehru National Institute of Technology Research Scholor
  2018 - Present

Education

• Motilal Nehru National Institute of Technology M.Tech
  2012 - 2014

Projects & Funding

Projects & funding information is unavailable.

Publications (12)

• Design and Analysis of Negative Capacitance Graded Channel Junctionless Nanowire for Analog/RF Applications
  Lecture Notes in Electrical Engineering 2023 DOI: 10.1007/978-981-99-0973-5_61
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• Low-Frequency Noise Characterization and Thermal Stability Analysis of Negative Capacitance Junction-Less Transistors
  Integrated Ferroelectrics 2023 DOI: 10.1080/10584587.2023.2173441
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• Performance Investigation of Graded channel and Dual-Metal Gate-Stack DG MOSFET
  5th International Conference on Power, Control and Embedded Systems, ICPCES 2023 2023 DOI: 10.1109/ICPCES57104.2023.10075985
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• A Novel Approach to Investigate Analog and Digital Circuit Applications of Silicon Junctionless-Double-Gate (JL-DG) MOSFETs
  Silicon 2022 DOI: 10.1007/S12633-021-01520-7
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• Analysis and Study of L-Shaped Dielectric Pocket and Its Effect on the Performance of MOSFET in Nano Scale Regime
  2022 IEEE Students Conference on Engineering and Systems, SCES 2022 2022 DOI: 10.1109/SCES55490.2022.9887677
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• Analysis of Negative Capacitance Double-Gate Junctionless Transistor for the Variation of Device Parameters
  Lecture Notes in Electrical Engineering 2022 DOI: 10.1007/978-981-16-2761-3_24
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• Comparative Analysis & Study of Various Leakage Reduction Techniques for Short Channel Devices in Junctionless Transistors: A Review and Perspective
  Silicon 2022 DOI: 10.1007/S12633-021-01181-6
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• Linearity Distortion & Thermal Stability Analysis of Negative Capacitance based Cylindrical Junction-less Transistors (NC-CyJLT)
  Silicon 2022 DOI: 10.1007/s12633-022-01662-2
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• Power Optimized 7 T SRAM Cell with Single Bit Line Using FinFET Technology
  Lecture Notes in Electrical Engineering 2022 DOI: 10.1007/978-981-19-2631-0_49
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• A Novel Approach to Investigate Analog and Digital Circuit Applications of Silicon Junctionless-Double-Gate (JL-DG) MOSFETs
  Research Square 2021 DOI: 10.21203/rs.3.rs-933781/v1
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