Sukarn Agarwal

Employment

• Indian Institute of Science Education and Research, Bhopal Assistant Professor
  2024 - Present
• Indian Institute of Technology Mandi Assistant Professor
  2023 - 2024
• University of Edinburgh Research Associate
  2021 - 2023
• Indian Institute of Technology BHU Assistant Professor
  2020 - 2021
• Persistent Systems Ltd Software Developer
  2013 - 2014

Education

• Indian Institute of Technology Guwahati Ph.D.
  2014 - 2020
• Madhav Institute of Technology and Science Bachelor of Engineering
  2009 - 2013

Projects & Funding

Projects & funding information is unavailable.

Publications (25)

• PRECIOUS: Approximate Real-Time Computing in MLC-MRAM Based Heterogeneous CMPs
  IEEE Transactions on Computers 2025 DOI: 10.1109/TC.2025.3590809
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• ARCTIC: Approximate Real-Time Computing in a Cache-Conscious Multicore Environment
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2024 DOI: 10.1109/TCAD.2024.3384442
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• TEEMO: Temperature Aware Energy Efficient Multi-Retention STT-RAM Cache Architecture
  2024 IEEE International Parallel and Distributed Processing Symposium (IPDPS) 2024 DOI: 10.1109/ipdps57955.2024.00080
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• Architecting Selective Refresh based Multi-Retention Cache for Heterogeneous System (ARMOUR)
  2023 60th ACM/IEEE Design Automation Conference (DAC) 2023 DOI: 10.1109/dac56929.2023.10247878
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• Compound Memory Models
  Proceedings of the ACM on Programming Languages 2023 DOI: 10.1145/3591267
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• DELICIOUS: Deadline-Aware Approximate Computing in Cache-Conscious Multicore
  IEEE Transactions on Parallel and Distributed Systems 2023 DOI: 10.1109/TPDS.2022.3228751
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• DAMUS: Dynamic Allocation based on Write Frequency in MUlti-Retention STT-RAM based Last Level Caches
  2021 22nd International Symposium on Quality Electronic Design (ISQED) 2021 DOI: 10.1109/isqed51717.2021.9424250
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• ABACa: Access based allocation on set wise multi-retention in STT-RAM last level cache
  Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors 2021 DOI: 10.1109/ASAP52443.2021.00032
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• Improving the Performance of Hybrid Caches Using Partitioned Victim Caching
  ACM Transactions on Embedded Computing Systems 2021 DOI: 10.1145/3411368
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• DidaSel: Dirty data based selection of VC for effective utilization of NVM buffers in on-chip interconnects
  ACM International Conference Proceeding Series 2020 DOI: 10.1145/3370748.3406565
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