0000-0003-1407-4492 Employment
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Publications (10)
- Fast 3D integrated circuit placement methodology using merging technique Save
- Cut-less technology mapping using shannon factor graph with on-the-fly size reduction Save
- Novel ASIC design flow using dynamic libraries for reducing design time Save
- Improved wire length-driven placement technique for minimizing wire length, area and timing Save
- A New Dynamic Library Based IC Design Automation Methodology Using Functional Symmetry with NPN Class Representation Approach to Reduce NRE Costs and Time-to-Market Save
- Effect of Constant One and Zero, Shared and Non-decomposed Nodes on Runtime and Graph Size of the Shannon Factor Graph (SFG) Save
- A new VLSI IC design automation methodology with reduced NRE costs and time-to-market using the NPN class Representation and functional symmetry Save
- A novel integrated circuit design methodology using Dynamic Library concept with reduced non-recurring engineering cost and time-to-market Save
- A novel and unified digital IC design and automation methodology with reduced NRE cost and time-to-market Save
- A novel physical synthesis methodology in the VLSI design automation by introducing dynamic library concept Save