Chandrashekhar Patil

Employment

• Cisco Systems (United States) Lead ASIC Engineering
  2013 - Present

Education

• B.M.S. College of Engineering Ph.D
  2018 - 2024
• SDM college of Engineering and Technology Mtech
  1998 - 2001

Projects & Funding

Projects & funding information is unavailable.

Publications (9)

• Enhancing Signoff DRC and Fill Workflows Using Calibre RealTime Digital
  2024
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• An Interposer
  Indian Patent office 2023
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• An Efficient Thermal Removal Solution for the Monolithic 2-D/2.5-D/3-D ICs
  IEEE explorer 2022
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• An alternative test method for the dual-port SRAM through the DesignWare SATA AHCI implementation in 3D IC structures
  Engineering Research Express 2022 DOI: 10.1088/2631-8695/ac44fd
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• Design and implementation of thermal collection networks in 3-D IC structures
  Heliyon 2022 DOI: 10.1016/j.heliyon.2022.e08719
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• A HEAT SINK FOR RAPID HEAT DISSIPATION
  Indian Patent office 2021
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• Compact modeling of through silicon vias for thermal analysis in 3-D IC structures
  Sadhana - Academy Proceedings in Engineering Sciences 2021 DOI: 10.1007/s12046-020-01549-1
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• Turtle Base with Fin Perforated Heat Exchangers for the 2.5D and 3D IC Structures
  10TH INTERNATIONAL MICROSYSTEMS, PACKAGING, ASSEMBLY AND CIRCUITS TECHNOLOGY CONFERENCE (IMPACT) on October 25, 2017 2015
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• Leakage power reduction in CMOS circuits
  USA Patent Office -US8018003B2 2005
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