JJ
Jaewon Jang
Kyungpook National University, Samsung Advanced Institute of Technology, UC Berkely, University of California, Berkeley
Research areas: Engineering · Electrical and Electronic Engineering · Thin-Film Transistor Technologies · Organic Electronics and Photovoltaics · Semiconductor materials and devices
Employment
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Kyungpook National University Assistant Prof.2016 - Present
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Samsung Advanced Institute of Technology Researcher2015 - 2016
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UC Berkeley Post Doc. Researcher2014 - 2015
Education
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UC Berkely pH. D.2008 - 2013
Projects & Funding
Projects & funding information is unavailable.
Publications (29)
- Effects of Annealing Temperature Combinations in InOx/AlOx Heterostructure for High-Performance and Stable Solution-Processed Junctionless Transistors Save
- Improving the Nonvolatile Memory Characteristics of Sol–Gel-Processed Y2O3 RRAM Devices Using Mono-Ethanolamine Additives Save
- UV/Ozone-Treated and Sol–Gel-Processed Y2O3 Insulators Prepared Using Gelation-Delaying Precursors Save
- Dependence of Positive Bias Stress Instability on Threshold Voltage and Its Origin in Solution-Processed Aluminum-Doped Indium Oxide Thin-Film Transistors Save
- Effect of Electrochemically Active Top Electrode Materials on Nanoionic Conductive Bridge Y2O3 Random-Access Memory Save
- Low-Temperature Enhancement-Mode Amorphous Oxide Thin-Film Transistors in Solution Process Using a Low-Pressure Annealing Save
- Sol–Gel-Processed Y2O3 Multilevel Resistive Random-Access Memory Cells for Neural Networks Save
- Sol–Gel-Processed Y2O3–Al2O3 Mixed Oxide-Based Resistive Random-Access-Memory Devices Save
- Simulation of Capacitorless DRAM Based on the Polycrystalline Silicon Nanotube Structure with Multiple Grain Boundaries Save
- Improvement in Switching Characteristics and Bias Stability of Solution-Processed Zinc–Tin Oxide Thin Film Transistors via Simple Low-Pressure Thermal Annealing Treatment Save
- Improved Tunneling Property of p+Si Nanomembrane/n+GaAs Heterostructures through Ultraviolet/Ozone Interface Treatment Save
- Design of a Capacitorless DRAM Based on Storage Layer Separated Using Separation Oxide and Polycrystalline Silicon Save
- Design of a Capacitorless DRAM Based on a Polycrystalline-Silicon Dual-Gate MOSFET with a Fin-Shaped Structure Save
- Improved Environment Stability of Y2O3 RRAM Devices with Au Passivated Ag Top Electrodes Save
- Physico-Chemical Origins of Electrical Characteristics and Instabilities in Solution-Processed ZnSnO Thin-Film Transistors Save
- Importance of Structural Relaxation on the Electrical Characteristics and Bias Stability of Solution-Processed ZnSnO Thin-Film Transistors Save
- Enhanced Switching Reliability of Sol–Gel-Processed Y2O3 RRAM Devices Based on Y2O3 Surface Roughness-Induced Local Electric Field Save
- Flexible Sol-Gel—Processed Y2O3 RRAM Devices Obtained via UV/Ozone-Assisted Photochemical Annealing Process Save
- Improved Negative Bias Stress Stability of Sol–Gel-Processed Li-Doped SnO2 Thin-Film Transistors Save
- Improving of Sensitivity of PbS Quantum Dot Based SWIR Photodetector Using P3HT Save