Siddharth Kala

About

R. K. SIDDHARTH (Member, IEEE) was born in Gujarat, India, in 1991. He received the B.E. degree in electronics and communication engineering from Government Engineering College, Patan, India, in 2013, and the M.Tech. and Ph.D. degrees in VLSI from the National Institute of Technology (NIT) Goa, India, in 2016 and 2021, respectively. His Ph.D. research focused on low-power and high-performance VLSI circuit techniques, with emphasis on memory architectures and analog-mixed-signal building blocks. Following his Ph.D. research, he continued at NIT Goa as a Research Associate, until July 2023, where he was actively involved in multiple sponsored and funded research projects, contributing to circuit design, system-level validation, and prototype development. From August 2023 to March 2025, he was an Assistant Professor with the Department of Mechatronics Engineering, Parul University, Gujarat. He subsequently completed his Postdoctoral Fellowship with the NIT Goa, in January 2026, further strengthening his research in energy-efficient analog and mixed-signal integrated circuit design. He is currently an Assistant Professor with Marwadi University, Rajkot, Gujarat. He has published more than 35 research papers in internationally reputed journals and conferences and has filed multiple patents based on his research outcomes. His primary research interests include low-power SRAM cells, analog and mixed-signal circuit design, data converters, high-speed comparators, and energy-efficient VLSI architectures. He serves as an Associate Editor for IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS

Employment

• Marwadi University Assistant Professor
  2026 - Present
• National Institute of Technology Goa Post-Doctoral Fellow
  2025 - 2026

Education

• National Institute of Technology Goa PhD
  2017 - 2021
• National Institute of Technology Goa Master of Technology
  2014 - 2016
• Government Engineering College Patan Bachelor of Engineering
  2009 - 2013

Projects & Funding

Projects & funding information is unavailable.

Publications (38)

• MFDFA-Enhanced GAN: A Hardware-Optimized Architecture for Efficient Synthetic Image Generation
  IEEE Access 2026 DOI: 10.1109/ACCESS.2026.3677066
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• A Power-Efficient High-Speed D-Latch Architecture for Enhanced PDP Performance
  IEEE ACCESS 2026 DOI: 10.1109/ACCESS.2026.3683583
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• A 0.9 V Configurable Dual Mode Comparator using a Supply Boosting Technique
  2025 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS 2025 DOI: 10.1109/ISCAS56072.2025.11043859
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• An energy-efficient D-latch architecture with feedforward technique for high-speed applications
  RESULTS IN ENGINEERING 2025 DOI: 10.1016/J.RINENG.2025.107301
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• Evolutionary-Enhanced GAN With Wavelet-Based Discrimination: A Hardware-Accelerated Architecture for Efficient Synthetic Image Generation
  IEEE Access 2025 DOI: 10.1109/ACCESS.2025.3642041
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• Generating Synthetic Data Using 2D Multifractal Detrended Fluctuation Analysis Generative Adversarial Networks
  IEEE Access 2025 DOI: 10.1109/ACCESS.2025.3603332
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• An exponential variation based PSO for analog circuit sizing in constrained environment
  AEU - International Journal of Electronics and Communications 2024 DOI: 10.1016/j.aeue.2024.155531
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• A 1.2 V Single Event Multinode Upset Tolerant RHSC 12T Memory Cell in 65-nm CMOS
  IEEE TRANSACTIONS ON ELECTRON DEVICES 2024 DOI: 10.1109/TED.2023.3343316
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• An Error Bound Particle Swarm Optimization for Analog Circuit Sizing
  IEEE ACCESS 2024 DOI: 10.1109/ACCESS.2024.3385491
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• N-Parallel Paths-Based D-Latch for High-Speed Applications
  IEEE Access 2024 DOI: 10.1109/ACCESS.2024.3491577
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