Anshul Verma

About

I am a dedicated research scholar at the Indian Institute of Technology (IIT) Roorkee with a strong background in Analog, RF, and Mixed-signal circuit design. My expertise lies in Phase-Locked Loop (PLL) design, SAR ADC design, bandgap reference circuits, and current reference designs. I have hands-on experience in tape-outs using 65nm technology and have worked extensively with CMOS technologies, including 180nm, 65nm, and 28nm, using Cadence Virtuoso for circuit and layout design.
In addition to my IC design skills, I have experience in PCB design, and I am proficient in embedded C programming with practical experience in ATMEL microcontrollers.
Driven by a passion for cutting-edge research and technology, I continuously strive to innovate and contribute to advancements in the field of microelectronics and VLSI.

Employment

Employment history is unavailable.

Education

• Indian Institute of Technology Roorkee Ph.D.
  2019 - 2026
• Indian Institute of Information Technology M.Tech. Microelectronics
  2017 - 2019
• University Institute of Engineering and Technology, Chhatrapati Shahu Ji Maharaj University B.Tech
  2012 - 2016

Projects & Funding

Projects & funding information is unavailable.

Publications (6)

• A Low-Jitter and Spur Dual-Edge Sub-Sampling Phase-Locked Loop With Double-Balanced Sampling Mixer-Adopted Phase Detector
  IEEE Transactions on Microwave Theory and Techniques 2025 DOI: 10.1109/TMTT.2025.3592277
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• An Ultra-Low Jitter Divider-Less Phase-Locked Loop using Differential Dual-Edge Sub-Sampling Phase Detector
  2025 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, APCCAS 2025 DOI: 10.1109/APCCAS67402.2025.11376831
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• A Low Power Dual-Band Sub-Sampling Phase Locked Loop with sub-100 fs RMS Jitter and & <-255-dB FOMjitter
  2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID) 2024 DOI: 10.1109/vlsid60093.2024.00032
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• A Peak-detector-based Ultra Low Power ECG ASIC for Early Detection of Cardio-Vascular Diseases
  IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS 2024 DOI: 10.1109/ISCAS58744.2024.10558031
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• Ultra-Low Power Non-Uniform SAR ADC based ECG detector for Early Detection of Cardiovascular Diseases
  2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID) 2023 DOI: 10.1109/vlsid57277.2023.00032
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• Low Power Dual-Band Current Reuse-based LC-Voltage Controlled Oscillator with Shared Inductor for IoT Applications
  Communications in Computer and Information Science 2022 DOI: 10.1007/978-3-031-21514-8_17
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