DHEERAJ KALRA

About

Dheeraj Kalra obtained his Master degree in Information and Communication Technology from GLA University, Mathura, India. He is currently pursuing Ph.D. from NIT Jamshedpur, India. His areas of interest include Radio Frequency Integrated Circuit Design and other latest trends in technology. He has more than 11 years of experience in teaching and research in the area of integrated circuits.

Employment

• National Institute of Technology Jamshedpur Research Scholar
  2019 - Present

Education

Education history is unavailable.

Projects & Funding

Projects & funding information is unavailable.

Publications (9)

• Optimizing Bio-Sensor Design With Support Vector Regression Technique for AlGaN/GaN MOS–HEMT
  IEEE Sensors Letters 2023 DOI: 10.1109/LSENS.2023.3307064
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• Low noise amplifier for high frequency applications: A review
  Materials Today: Proceedings 2023 DOI: 10.1016/j.matpr.2023.03.354
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• A triple path noise cancellation LNA with transformer output using 45 nm CMOS technology
  Journal of Electrical Engineering 2022 DOI: 10.2478/jee-2022-0045
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• Design and performance analysis of low power LNA with variable gain current reuse technique
  Analog Integrated Circuits and Signal Processing 2021 DOI: 10.1007/s10470-021-01855-6
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• Design Analysis of Inductorless Active Loaded Low Power UWB LNA Using Noise Cancellation Technique
  Frequenz 2020 DOI: 10.1515/freq-2019-0080
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• Realization of Low Noise Amplifier for 1-5 GHz Using Noise Cancellation Technique
  2020 International Conference on Power Electronics & IoT Applications in Renewable Energy and its Control (PARC) 2020 DOI: 10.1109/parc49193.2020.236658
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• Improved 0.18μm CMOS down-conversion mixer for UWB systems
  2017 8th International Conference on Computing, Communication and Networking Technologies (ICCCNT) 2017 DOI: 10.1109/icccnt.2017.8204103
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• Design of low power UWB LNA for frequency 3.1–5 GHz in 0.18 μm CMOS technology
  International Conference on Computing, Communication & Automation 2015 DOI: 10.1109/ccaa.2015.7148371
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• A 3.1-10.6 GHz CMOS down-conversion mixer for UWB system
  2014 International Conference on Signal Processing and Integrated Networks (SPIN) 2014 DOI: 10.1109/spin.2014.6777017
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