Tarun Kumar Sharma

About

Tarun Kumar Sharma received his B.Tech in Electronics and Communication Engineering from Jalpaiguri Govt. Engg. College (WBUT), West Bengal, India in the year 2009 and M.Tech in Electrical Engineering (Mechatronics) from NITTTR, Kolkata in the year 2013 respectively. He is pursuing his Ph.D. in Electronics and Communication Engineering Dept. as a Full-Time Ph.D. scholar at Indian Inst. of Technology (ISM), Dhanbad, India and is a member of IEEE (Institute of Electrical and Electronics Engineers). His current research areas include the Nanoscale Devices, Gate-All-Around (GAA) MOSFET modeling, TCAD Simulation, Strained MOSFET, Parasitic Capacitance Effects and Performance evaluation of SWCNT Interconnects using GAA Drivers, Memristors, Neuromorphic Circuit, SNN etc. To his credit, he has contributed his work in reputed journals and conferences in the fields of Nanoscale MOSFET devices modeling and simulations.

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Publications (5)

• Compact Memristor Emulator with SDDP for Integrated Neuromorphic Temporal Learning
  IEEE Transactions on Circuits and Systems for Artificial Intelligence 2026 DOI: 10.1109/tcasai.2026.3676004
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• On-Chip Carbon Nanotube Interconnects: Adaptation to Multi-gate Transistors
  Carbon Related Materials 2020 DOI: 10.1007/978-981-15-7610-2_7
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• On the C-V characteristics of nanoscale strained gate-all-around Si/SiGe MOSFETs
  Solid-State Electronics 2019 DOI: 10.1016/j.sse.2019.02.006
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• A comparative study of above-and sub-threshold characteristics of strained and unstrained Si GAA MOSFETs
  2018 International Symposium on Devices, Circuits and Systems, ISDCS 2018 2018 DOI: 10.1109/ISDCS.2018.8379655
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• Impact of geometry aspect ratio on the performance of si GAA nanowire MOSFET
  2017 International Conference on Microelectronic Devices, Circuits and Systems, ICMDCS 2017 2017 DOI: 10.1109/ICMDCS.2017.8211534
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