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Publications (9)
- Design of an area and energy-efficient last-level cache memory using STT-MRAM Save
- Effect of gate length on performance of 5nm node N-channel nano-sheet transistors for analog circuits Save
- IWT Based Iris Recognition for Image Authentication Save
- Impact of Size, Latency of Cache-L1 and Workload over System Performance Save
- Mixed-mode circuit simulations with 5 nm Node Nanosheet Transistors using TCAD Save
- Classification of human heart signals by novel feature extraction techniques for rescue application Save
- Novel feature extraction algorithm using DWT and temporal statistical techniques for word dependent speaker's recognition Save
- On efficient minimization techniques of logical constituents and sequential data transmission for digital IC Save
- Influence of grains and surface roughness in boron and phosphorus implanted LPCVD polycrystalline silicon thin film Save