Narendra Singh Dhakad

About

Dr. Narendra received his Bachelor of Engineering (BE) from Indira Gandhi Government Engineering College (IGEC), Sagar, Master of Technology (MTech) from Shri G. S. Institute of Technology and Science (SGSITS), Indore, and PhD from Indian Institute of Technology (IIT) Indore, India. His research interests lie broadly in the areas of in-memory computing for AI hardware, emerging memory devices, and architectures.

He was an Assistant Professor at Shri G. S. Institute of Technology and Science, Indore, India, from June 2018 to November 2019. He worked as a Lecturer at Indira Gandhi Government Engineering College, Sagar, from July 2017 to May 2018. He was Visiting Research Fellow at Purdue University, USA for one year. He worked as a Processor Architecture Research Intern at Intel Labs, Bangalore and as a Postdoctoral Researcher at the Chair of AI Processor Design, Technical University of Munich (TUM), Germany, from August 2024 to June 2025.

He was the Founding Co-Chair of the IEEE Circuits And Systems Society (CASS) Madhya Pradesh Section, Founding Chair of the IEEE Circuits And Systems Society (CASS) Student Chapter and Founding Head of Outreach Activity and Webmaster of the IEEE Nanotechnology Council (NTC) Student Chapter at IIT Indore. He serves as a reviewer for several top-tier journals, including IEEE Transactions on Circuits and Systems I: Regular Papers, IEEE Transactions on Very Large Scale Integration Systems, IEEE Embedded Systems Letters, Circuits, Systems, and Signal Processing (CSSP), Springer and Scientific Reports, Springer Nature.

Employment

• Intel (India) PDK Engineer
  2025 - Present
• Technical University of Munich Postdoctoral Researcher
  2024 - 2025
• Intel (India) Research Intern
  2024 - 2024
• Shri G. S. Institute of Technology and Science Assistant Professor
  2018 - 2019
• Indira Gandhi Government Engineering College Sagar Lecturer
  2017 - 2018

Education

• Indian Institute of Technology Indore PhD
  2019 - 2024

Projects & Funding

Projects & funding information is unavailable.

Publications (15)

• RAPID: Re-Configurable Adder Tree Based Performance-Incentivized AI Digital CIM Macro
  IEEE Transactions on Nanotechnology 2026 DOI: 10.1109/TNANO.2026.3680063
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• Configurable Multiport Memory Architecture for High-Speed Data Communication
  IEEE Embedded Systems Letters 2025 DOI: 10.1109/LES.2024.3485509
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• FlexDCIM: A 400 MHz 249.1 TOPS/W 64 Kb Flexible Digital Compute-in-Memory SRAM Macro for CNN Acceleration
  IEEE Transactions on Circuits and Systems I: Regular Papers 2025 DOI: 10.1109/TCSI.2025.3547853
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• ReCAM: Resistive RAM Digital Content Addressable Memory Using Novel 3T1R Bitcell
  2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM) 2024 DOI: 10.1109/edtm58488.2024.10511788
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• Memristor-Inspired Digital Logic Circuits and Comparison With 90-/180-nm CMOS Technologies
  IEEE Transactions on Electron Devices 2024 DOI: 10.1109/TED.2023.3278625
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• Combinational logic circuits based on a power- and area-efficient memristor with low variability
  Journal of Computational Electronics 2023 DOI: 10.1007/s10825-023-02117-6
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• A Configurable Activation Function for Variable Bit-Precision DNN Hardware Accelerators
  Internet of Things. Advances in Information and Communication Technology 2023 DOI: 10.1007/978-3-031-45878-1_31
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• R-inmac: 10T SRAM based reconfigurable and efficient in-memory advance computation for edge devices
  Analog Integrated Circuits and Signal Processing 2023 DOI: 10.1007/s10470-023-02181-9
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• In-Memory Computing with 6T SRAM for Multi-operator Logic Design
  Circuits, Systems, and Signal Processing 2023 DOI: 10.1007/s00034-023-02481-5
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• BitMAC: Bit-Serial Computation-Based Efficient Multiply-Accumulate Unit for DNN Accelerator
  Circuits, Systems, and Signal Processing 2022 DOI: 10.1007/s00034-021-01873-9
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