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Bandan Bhoi
Veer Surendra Sai University of Technology, International Institute of Information Technology Hyderabad
0000-0003-2916-2903
Employment
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Veer Surendra Sai University of Technology Assistant Professor2011 - Present
Education
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International Institute of Information Technology Hyderabad M.Tech2008 - 2010
Projects & Funding
Projects & funding information is unavailable.
Publications (28)
- Signed multiplication architecture using Vedic Urdhva Tiryagbhyam algorithm Save
- Design and Analysis of Area and Time Efficient Signed Square Architecture Using Nonconventional Method Save
- Nanotechnology QCA-based sub-components of processor design and application of futuristic low-power design Save
- Utilizing a Novel Universal Quantum Gate in the Design of Fault-Tolerant Architecture Save
- Компресор 3:2 з низьким енергоспоживанням на основі XOR-XNOR та 2:1 мультиплексора за QCA технологією Save
- Low-energy 3:2 Compressor Using XOR-XNOR Gate Combined with 2:1 Multiplexer in QCA Technology Save
- Efficient architecture for arithmetic designs using perpendicular NanoMagnetic Logic Save
- Оптимизация параметров сумматоров и устройства быстрого сдвига на основе технологии QCA Save
- Fast signed multiplier using Vedic Nikhilam algorithm Save
- A Redundant Adder Architecture in Ternary Quantum-Dot Cellular Automata Save