Aniruddha Konar
Also known as: A.Konar
Research areas: Engineering · Electrical and Electronic Engineering · Advancements in Semiconductor Devices and Circuit Design · 2D Materials and Applications · Semiconductor materials and devices
0000-0003-2972-059X
About
Aniruddha Konar is a TCAD Software Research Scientist in Intel, where he supports Technology development of advanced transistor node beyond 2nm. He has held positions in Synopdys,India ( code development), SAIT, Samsung Research Institute, GLOBALFOUNDRIES and IBM Semiconductor R&D Center, Bangalore. He holds a PhD degree in Physics/EE from University of Notre Dame, USA and published various technical papers and patents. His primary work area is Semiconductor Physics and transport in semiconductors and metals, technology development and scientific code development.
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Publications (37)
- Surface roughness mediated specularity parameter of thin Cu films Save
- Non-specular scattering of carriers from surface defects in thin metal interconnects Save
- Electrical resistivity of atomically smooth single-crystal Cu films Save
- Improved statistical variability and delay performance with junctionless inserted oxide FinFET Save
- Optimized Substrate for Improved Performance of Stacked Nanosheet Field-Effect Transistor Save
- Analyzing the impact of grain boundary scattering on the metal resistivity: First-principles study of symmetric tilt grain boundaries in copper Save
- Impact of geometrical parameters and substrate on analog/RF performance of stacked nanosheet field effect transistor Save
- Random dopant fluctuations impact reduction in 7 nm bulk-FinFET by substrate engineering Save
- Leakage aware Si/SiGe CMOS FinFET for low power applications Save
- Carrier transport in layered nanolaminated carbides Save
- First-Principles Investigations of TiGe/Ge Interface and Recipes to Reduce the Contact Resistance Save
- How thin barrier metal can be used to prevent Co diffusion in the modern integrated circuits? Save
- Interface engineering of Si<inf>1-x</inf>Ge<inf>x</inf> gate stacks for high performance dual channel CMOS Save
- Selective GeO<inf>x</inf>-scavenging from interfacial layer on Si<inf>1-x</inf>Ge<inf>x</inf> channel for high mobility Si/Si<inf>1-x</inf>Ge<inf>x</inf> CMOS application Save
- Carrier transport in high mobility InAs nanowire junctionless transistors Save
- Erratum: Tunneling-triggered bipolar action in junctionless tunnel field-effect transistor (Appl. Phys. Express (2014) 7 (124302)) Save
- CMOS logic device and circuit performance of Si gate all around nanowire MOSFET Save
- Negative differential conductivity and carrier heating in gate-all-around Si nanowire FETs and its impact on CMOS logic circuits Save
- Tunneling-triggered bipolar action in junctionless tunnel field-effect transistor Save
- Dielectric-environment mediated quantum screening of two-dimensional electron gas Save