Debashish Nandi

About

Mr. Debashish Nandi is an Electrical Engineer with specialization in Microelectronics and VLSI. He holds a B.Tech degree in Electronics and Communication Engineering from NIT Durgapur, India and is currently pursuing PhD in Microelectronics and VLSI from IIT Kanpur, India. He has an industry experience of four years in Telecommunication systems' design and integration with a focus to Railways, Metro and Urban transit systems. He is recipient of several national level and state level scholarships for his academic achievements.

Employment

• Larsen & Toubro (India) Asst. Manager (E&C)
  2017 - 2021

Education

• Indian Institute of Technology Kanpur PhD (pursuing)
  2022 - 2026
• National Institute of Technology Durgapur Bachelor of Technology
  2013 - 2013

Projects & Funding

Projects & funding information is unavailable.

Publications (12)

• Nonlinear Body Resistance in SOI MOSFETs Under Dynamic Depletion: Compact Modeling and DC Characterization
  IEEE Transactions on Electron Devices 2026 DOI: 10.1109/TED.2026.3652538
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• Characterization and Modeling of Fully Depleted SOI Varactor With Independently Controlled Front- and Back-Gates for RF Applications
  IEEE Transactions on Electron Devices 2025 DOI: 10.1109/TED.2025.3566930
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• Impact Ionization in LDMOS Transistors: Improved Compact Model and Asymmetry Under Forward and Reverse Modes of Operation
  IEEE Journal of the Electron Devices Society 2025 DOI: 10.1109/JEDS.2025.3529730
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• Modeling of Gate-Induced-Drain-Leakage Under Low Electric Field in FDSOI MOSFETs
  IEEE Transactions on Electron Devices 2025 DOI: 10.1109/TED.2025.3601574
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• Utilizing Symmetric BSIM-SOI SPICE Model for Dynamically Depleted RF SOI T/R Switches and Logic Circuits
  IEEE Journal of the Electron Devices Society 2025 DOI: 10.1109/JEDS.2024.3484295
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• Physical Insights and Accurate Modeling of Transconductance in Body-Contacted Dynamically Depleted SOI MOSFETs
  IEEE Transactions on Electron Devices 2024 DOI: 10.1109/TED.2024.3461670
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• Compact Modeling and Experimental Validation of Reverse Mode Impact Ionization in LDMOS Transistors within the BSIM-BULK Framework
  IEEE Electron Devices Technology and Manufacturing Conference (EDTM) 2024 DOI: 10.1109/EDTM58488.2024.10512085
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• Symmetric BSIM-SOI-Part I: A Compact Model for Dynamically Depleted SOI MOSFETs
  IEEE Transactions on Electron Devices 2024 DOI: 10.1109/TED.2024.3363110
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• Symmetric BSIM-SOI-Part II: A Compact Model for Partially Depleted SOI MOSFETs
  IEEE Transactions on Electron Devices 2024 DOI: 10.1109/TED.2024.3363117
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• Validation of Dynamically Depleted Symmetric BSIM-SOI Compact model for RF SOI T/R Switch Applications
  IEEE Electron Devices Technology and Manufacturing Conference (EDTM) 2024 DOI: 10.1109/EDTM58488.2024.10512295
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