Sukanta Dey

About

Sukanta is working as a Senior EDA Engineer at Intel Corporation, Santa Clara, CA. Previously, he was a Postdoctoral Research Associate at the Department of Electrical and Computer Engineering (ECE), University of Florida, Gainesville, FL, US. He received his Master’s and Ph.D. from the Department of Computer Science and Engineering, IIT Guwahati in March 2021, specializing in Machine Learning techniques for Electronic Design Automation (EDA). His Ph.D. thesis title is "Design Methodology for On-Chip Power Grid Interconnect: AI/ML Perspective". Prior to joining IIT Guwahati, he received his Bachelor's in Electronics and Telecommunication Engineering from Assam Engineering College in July 2014. His domain of expertise includes EDA, VLSI CAD, VLSI Physical Design, Machine Learning for VLSI CAD, Custom IC Design (Analog and Mixed Signal), RTL to GDS2 Flow (ASIC Design), and Hardware Security/Security-Aware EDA.

Employment

• Intel Corporation Senior EDA Engineer
  2023 - Present
• University of Florida Postdoctoral Research Associate
  2021 - 2023
• Indian Institute of Technology Guwahati Research Scholar
  2014 - 2021

Education

• Indian Institute of Technology Guwahati M.Tech & Ph.D.
  2014 - 2021
• Assam Engineering College Bachelor of Engineering
  2010 - 2014

Projects & Funding

Projects & funding information is unavailable.

Publications (16)

• Secure Physical Design
  2022
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• Machine Learning for VLSI CAD: A Case Study in On-Chip Power Grid Design
  2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2021 DOI: 10.1109/isvlsi51109.2021.00075
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• Design Methodology for On-Chip Power Grid Interconnect: Al/ML Perspective
  Ph.D. dissertation 2021
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• PGOpt: Multi-objective Design Space Exploration Framework for Large-Scale On-Chip Power Grid Design in VLSI SoC using Evolutionary Computing Technique
  Microprocessors and Microsystems 2020 DOI: 10.1016/j.micpro.2020.103440
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• Machine Learning Approach for Fast Electromigration Aware Aging Prediction in Incremental Design of Large Scale On-chip Power Grid Network
  ACM Transactions on Design Automation of Electronic Systems 2020 DOI: 10.1145/3399677
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• PowerPlanningDL: Reliability-Aware Framework for On-Chip Power Grid Design using Deep Learning
  2020 Design, Automation & Test in Europe Conference & Exhibition (DATE) 2020 DOI: 10.23919/date48585.2020.9116536
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• Energy Efficient Approach to Detect Sinkhole Attack Using Roving IDS in 6LoWPAN Network
  Innovations for Community Services 2020 DOI: 10.1007/978-3-030-37484-6_11
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• PGRDP: Reliability, Delay, and Power-Aware Area Minimization of Large-Scale VLSI Power Grid Network Using Cooperative Coevolution
  2020 DOI: 10.1007/978-981-13-7334-3_6
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• ReFIT: Reliability Challenges and Failure Rate Mitigation Techniques for IoT Systems
  2020 DOI: 10.1007/978-3-030-37484-6_7
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• RiverOpt: A Multiobjective Optimization Framework Based on Modified River Formation Dynamics Heuristic
  2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID) 2019 DOI: 10.1109/vlsid.2019.00059
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