Bharath Sreenivasulu Vakkalakula -- IIT Patna- VLSI-- Postdoc
IIT Patna, REVA University, Vellore Institute of Technology University
About
Myself Bharath Sreenivasulu presently working as an postdoctoral Research Associate in IIT Patna. I have done PHD in VLSI devices and circuits from NIT Warangal. I have qualified UGC-NET (99.18%), GATE (AIR) - 6898, APRSET qualified. I have done my B.Tech in MITS/JNTUA Madanapalle in ECE with 81% (Topper), M.tech in G. Pulla reddy engineering college/JNTUA in VLSI with 84% (Goldmedal). Worked in MITS madanapalle, as Assistant professor, placement coordinator in ECE dept from oct-2016 to dec 2018. Worked as Sr. Assistant Professor in VIT University, India from Apr-2022 to Apr-2023.
Presently I am technical reviewer of following Journals:
(a)ECS IOP
(b)AEU
(c)SST IOP
(c)Microelectronics Journal
(d) International Journal of RF and Microwave Computer-Aided Engineering (Wiley)
(e)Silicon
(f)Materials today proceedings
(g) IEEE Transactions on Electronic Devices
(i) Nature -Scientific Reports
Employment
-
IIT Patna Postdoctoral Researcher2023 - Present
-
REVA University Sr Assistant professor2023 - 2024
-
Vellore Institute of Technology University Sr Assistant Professor2022 - 2023
-
National Institute of Technology Warangal Research Scholar2018 - 2022
-
Madanapalle Institute of Technology and Science Assistant Professor2016 - 2018
Education
Education history is unavailable.
Projects & Funding
Projects & funding information is unavailable.
Publications (29)
- Gate Stack Analysis of Junctionless Multi-Bridge-Channel FETs for Sub-3 nm Chips Save
- DC and RF performance analysis of enhancement mode fin-shaped tri-gate AlGaN/GaN HEMT and MOSHEMT with ultra-thin barrier layer Save
- Benchmarking of Multi-Bridge-Channel FETs Toward Analog and Mixed-Mode Circuit Applications Save
- Performance Comparison of Nanosheet FET, CombFET, and TreeFET: Device and Circuit Perspective Save
- Performance Improvement of Spacer-Engineered N-Type Tree Shaped NSFET Toward Advanced Technology Nodes Save
- Spacer Dielectric Analysis of Multi-Channel Nanosheet FET for Nanoscale Applications Save
- Nanosheet Field Effect Transistor Device and Circuit Aspects for Future Technology Nodes Save
- Common Source Amplifier and Ring Oscillator Circuit Performance Optimization Using Multi-Bridge Channel FETs Save
- Impact of Scaling on Nanosheet FET and CMOS Circuit Applications Save
- Design of approximate reverse carry select adder using RCPA Save