About
Assistant professor, Jamia Millia Islamia, New Delhi, India
Employment
Employment history is unavailable.
Education
-
Shri Mata Vaishno Devi University PhD2021 - 2024
Projects & Funding
Projects & funding information is unavailable.
Publications (31)
- Unbalanced Ternary Full Adder Architecture in CNTFET Technology: Design and Application Save
- Low Complexity, High-Performance Ternary Full Adder Using CNTFET Technology Save
- Design-Analysis of CNTFET-Based Energy Efficient Ternary Logic Gates Save
- Overcoming Silicon MOSFET Limitations with Chirality-Engineered CNTFETs: A Ternary Half Adder Demonstration for Next-Generation Nanoelectronics Save
- Hybrid Cross-Coupled Inverter-Based 8T SRAM Design With Half-Selection Immunity and Enhanced Stability for Power-Constrained Applications Save
- Energy-Efficient Buffer-Based Ternary SRAM Cell With Application to Image Processing Save
- An efficient design methodology for a tri-state multiplier circuit in carbon nanotube technology Save
- A stable, low-power SRAM cell with half-select immunity in CNTFET technology Save
- A Soft Error Self-Resilience Radiation-Hardened 14T SRAM for Aerospace Applications Save
- A CNTFET-Based 10T Static Memory Design Immune to Read and Half-Select Disturbs for Low-Power Wearable Biomedical Systems Save