0000-0003-3158-4013 About
Dr. Ramesh Vaddi has completed Ph.D. in Microelectronics and VLSI with the title” Robust and Ultra Low power Subthreshold logic: A Device/Circuit Co-Design” from Indian Institute of Technology Roorkee, India in 2010. He was a Senior Research Fellow with School of Computing, NUS Singapore during 2018-19, Postdoctoral Scholar in the Computer Science and Engineering Department at Pennsylvania State University, USA during Feb-August, 2013 and Postdoctoral Research Fellow in the School of Electrical and Electronic Engineering, Nanyang Technological University during the period Feb, 2011 - April, 2012. His research interests include hardware security, VLSI accelerators for ML, Energy efficient circuit design with Post-CMOS Transistors, etc. At Penstate, he has been involved in the Semiconductor Research Corporation (SRC) sponsored project “Centre for Low Energy Systems Technology (LEAST) and NSF sponsored Nanosystems Engineering Research Centre for Advanced Self-Powered Systems of Integrated Sensors and Technologies (ASSIST).
He has published research outcomes in several top IEEE conferences and peer reviewed International journals in device and circuits society and has about 50 research publications to his credit. He has few visiting researcher appointments and invited talks at various globally reputed institutes such as Hong Kong University of Science and Technology and Missouri University of Science and Technology (USA). He also has the experience of teaching some electrical and computer engineering courses such as Basic circuit theory, VLSI system design, Digital Electronics, CMOS analog and mixed signal VLSI, Digital design through VHDL/Verilog to UG and PG students at various reputed Engineering Institutes in India for about 6 years. Dr. Ramesh Vaddi is also presently serving as an editorial board member of a special issue of Journal of Microelectronics and Solid State Electronics, Scientific & Academic Publishing, USA and reviewer of IEEE Trans. on BioCAS, IEEE Trans. on VLSI systems, Elsevier Microelectronics Journal, Journal of Applied Physics, IOP Semiconductor Science and Technology and Technical committee member of Several IEEE International conferences such as ISCAS, ISLPED, ICM, ICCCIT, etc
Employment
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Education
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Publications (29)
- FeSATLock: An Energy Efficient and SAT Attack Resilient Logic Locking Design With FeFET LUT Architecture for Enhanced Hardware Security Save
- Computing in-memory reconfigurable (accurate/approximate) adder design with negative capacitance FET 6T-SRAM for energy efficient AI edge devices Save
- Low Area/Energy Consumption Overhead and Robust Logic Locking Designs for Hardware Obfuscation Exploring Negative Capacitance FETs with Circuit Co-Design Techniques Save
- Utilizing YOLO Models for Real-World Scenarios: Assessing Novel Mixed Defect Detection Dataset in PCBs Save
- A negative capacitance FET based energy efficient 6T SRAM computing-in-memory (CiM) cell design for deep neural networks Save
- Negative capacitance FET based energy efficient and DPA attack resilient ultra-light weight block cipher design Save
- Design and Performance Benchmarking of Hybrid Tunnel FET/STT-MTJ-Based Logic In-Memory Designs for Energy Efficiency Save
- Negative capacitance FETs for energy efficient and hardware secure logic designs Save
- Low area overhead DPA countermeasure exploiting tunnel transistor‐based random number generator Save
- Tunnel FET ambipolarity‐based energy efficient and robust true random number generator against reverse engineering attacks Save