Rajneesh Sharma

Employment

• Thapar Institute of Engineering and Technology

Education

• National Institute of Technology Hamirpur

Projects & Funding

Projects & funding information is unavailable.

Publications (14)

• Suppressed channel rectangular core-shell DG-JLFET for improved DC and analog performance
  Physica Scripta 2026 DOI: 10.1088/1402-4896/ae465d
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• Core-shell architecture and channel suppression: unleashing the potential of SC_RCS_DGJLFET
  Physica Scripta 2024 DOI: 10.1088/1402-4896/ad7aa8
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• Analysis of Underlap Strained Silicon on Insulator MOSFET for Accurate and Compact Modeling
  Silicon 2022 DOI: 10.1007/s12633-021-01059-7
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• Analysis of Underlap Strained Silicon on Insulator MOSFET for Accurate and Compact Modeling
  2021 DOI: 10.21203/rs.3.rs-182338/v1
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• Performance Evaluation of Negative Capacitance Junctionless FinFET under Extreme Length Scaling
  Silicon 2021 DOI: 10.1007/s12633-020-00931-2
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• Probabilistic Behavioural Model Based on X-parameters
  2020 IEEE Asia-Pacific Microwave Conference (APMC) 2020 DOI: 10.1109/apmc47863.2020.9331530
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• Analytical modelling of threshold voltage for underlap Fully Depleted Silicon-On-Insulator MOSFET
  International Journal of Electronics 2017 DOI: 10.1080/00207217.2016.1199052
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• Impact of High-k Spacer on Device Performance of Nanoscale Underlap Fully Depleted SOI MOSFET
  Journal of Circuits, Systems and Computers 2017 DOI: 10.1142/S0218126618500639
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• Impact of work function fluctuations on threshold voltage variability in a nanoscale FinFETs
  Proceedings - 2016 IEEE International Symposium on Nanoelectronic and Information Systems, iNIS 2016 2017 DOI: 10.1109/iNIS.2016.066
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• Line edge roughness induced threshold voltage variability in nano-scale FinFETs
  Superlattices and Microstructures 2017 DOI: 10.1016/j.spmi.2017.01.036
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