Dr. Pritha Banerjee

Employment

Employment history is unavailable.

Education

• Jadavpur University DST WISE Post Doctoral Fellow & Principal Investigator (DST WISE Project - 3 Years)

Projects & Funding

Projects & funding information is unavailable.

Publications (31)

• Exploring the parametric sensitivity of tubular channel junctionless stacked oxide gate-all-around MOSFET as ammonia gas detector: Analytical modeling and simulation
  Micro and Nanostructures 2026 DOI: 10.1016/j.micrna.2026.208617
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• Threshold voltage modeling based comparative performance exploration of Junctionless and Junction-Based High-K gate stack Dual-Material Cylindrical Gate-All-Around Macaroni MOSFET
  Materials Science and Engineering: B 2024 DOI: 10.1016/j.mseb.2024.117332
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• Analytical Exploration and Simulation of Dual-Material Gate Macaroni Channel MOSFET biosensor using dielectric-modulation technique
  Micro and Nanostructures 2022 DOI: 10.1016/j.micrna.2022.207196
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• Gate Work Function Engineered Trigate MOSFET with a Dual-Material Bottom Gate for Biosensing Applications: a Dielectric-Modulation Based Approach
  Silicon 2022 DOI: 10.1007/s12633-020-00823-5
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• Gate Work Function-Engineered Graded-Channel Macaroni MOSFET: Exploration of Temperature and Localized Trapped Charge-Induced Effects with GIDL Analysis
  Journal of Electronic Materials 2022 DOI: 10.1007/s11664-021-09419-0
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• Threshold voltage modeling of Gaussian-doped Dual work function Material Cylindrical Gate-all-around (CGAA) MOSFET considering the effect of temperature and fixed interface trapped charges
  Microelectronics Journal 2022 DOI: 10.1016/j.mejo.2021.105354
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• Interface Trap Charge Induced Threshold Voltage Modeling of WFE High-K SOI MOSFET
  Silicon 2020 DOI: 10.1007/s12633-020-00386-5
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• Impact of trapped interface charges on short channel characteristics of WFE high-K SOI MOSFET
  Proceedings of 3rd International Conference on 2019 Devices for Integrated Circuit, DevIC 2019 2019 DOI: 10.1109/DEVIC.2019.8783522
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• Two dimensional analytical modeling based threshold voltage characteristics of proposed linearly graded work function engineered gate all around SB MOSFET
  2018 International Conference on Computing, Power and Communication Technologies, GUCON 2018 2019 DOI: 10.1109/GUCON.2018.8675067
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• Surface potential based Analytical Modeling of Graded Channel Strained High-k Gate stack Dual-Material Double Gate MOSFET
  Proceedings of 3rd International Conference on 2019 Devices for Integrated Circuit, DevIC 2019 2019 DOI: 10.1109/DEVIC.2019.8783284
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