jean jenifer nesam

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Publications (5)

• Truncated Multiplier with Delay-Minimized Exact Radix-8 Booth Recoder Using Carry Resist Adder
  Circuits, Systems, and Signal Processing 2021 DOI: 10.1007/s00034-020-01559-8
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• Efficient half-precision floating point multiplier targeting color space conversion
  Multimedia Tools and Applications 2020 DOI: 10.1007/s11042-019-08040-y
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• High Speed Half-Precision Floating-Point Fused Multiply and Add Unit Using DSP Blocks
  Proceedings - 2020 1st International Conference of Smart Systems and Emerging Technologies, SMART-TECH 2020 2020 DOI: 10.1109/SMART-TECH49988.2020.00058
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• An area-efficient 32-bit floating point multiplier using hybrid GPPs addition
  2017 International Conference on Microelectronic Devices, Circuits and Systems, ICMDCS 2017 2017 DOI: 10.1109/ICMDCS.2017.8211573
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• An efficient single precision floating point multiplier architecture based on classical recoding algorithm
  Indian Journal of Science and Technology 2016 DOI: 10.17485/ijst/2016/v9i5/87159
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