Toral Shah

About

Toral Shah received her PhD in Electrical Engineering with specialization in VLSI Testing from Indian Institute of Technology Bombay, Mumbai, India. She received her Bachelors degree in Electronics Engineering from Sardar Patel College of Engineering(SPCE), Mumbai University, Mumbai, India, in 1999 and her M.E. degree in 2007 from Mumbai University. She has 15+ years of experience as faculty in Electronics Engineering at Mumbai University. Her research interests include delay testable synthesis, testable architectures, design-for-test, built-in-self-test, applications of scan based testing, applying concepts of VLSI testing to the field of physical security.

Employment

• School of Technology management and Engineering, NMIMS Navi Mumbai Campus Assistant Professor
  2019 - Present
• Mukesh Patel School of Technology Management and Engineering Assistant Professor
  2012 - 2012
• K. J. Somaiya College of Engineering Assistant Professor
  2002 - 2011
• Thadomal Shahani Engineering College Lecturer
  2000 - 2001

Education

• Indian Institute of Technology Bombay PhD
  2013 - 2018
• Sardar Patel College of Engineering Master of Engineering
  2005 - 2007
• Sardar Patel College of Engineering Bachelor of Engineering
  1996 - 1999
• Premlila Vithaldas Polytechnic Diploma
  1992 - 1996

Projects & Funding

Projects & funding information is unavailable.

Publications (8)

• Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design
  Journal of Electronic Testing (JETTA) 2018
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• Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design
  Journal of Electronic Testing Theory and Applications JETTA 2018 DOI: 10.1007/s10836-018-5703-3
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• Testing multiple stuck-at faults of ROBDD based combinational circuit design
  Test Symposium (LATS), 2017 18th IEEE Latin American 2017 DOI: 10.1109/LATW.2017.7906753
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• ROBDD based path delay fault testable combinational circuit synthesis
  2016 IEEE East-West Design & Test Symposium (EWDTS) 2017 DOI: 10.1109/EWDTS.2016.7807682
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• Test pattern generation to detect multiple faults in ROBDD based combinational circuits
  2017 IEEE 23rd International Symposium on on Line Testing and Robust System Design Iolts 2017 2017 DOI: 10.1109/IOLTS.2017.8046223
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• Multiple stuck-at fault testability of a combinational circuit derived by covering ROBDD nodes by Invert-And-Or sub-circuits
  Proceedings of 2015 IEEE East West Design and Test Symposium Ewdts 2015 2016 DOI: 10.1109/EWDTS.2015.7493099
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• PDF testability of a combinational circuit derived by covering ROBDD nodes using Invert-And-Or circuits
  2015 19th International Symposium on VLSI Design and Test 2015 DOI: 10.1109/ISVDAT.2015.7208130
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• Simplification of fully delay testable combinational circuits
  Proceedings of the 21st IEEE International on Line Testing Symposium Iolts 2015 2015 DOI: 10.1109/IOLTS.2015.7229829
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