0000-0003-4052-6253 Employment
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Publications (26)
- Design and Implementation of Modified Carry Select Adder Save
- Design and Implementation of Optimized Inexact Signed Wallace Tree Multiplier Using Reversible Logic Gates and 4:2 Compressors Save
- Performance Analysis of Dadda Multiplier Using Kogge Stone Adder Save
- A Novel Area Efficient and High-Speed BCD Adder Using CFA and Multiplexer in Quantum-Dot Cellular Automata Save
- An optimal cooperative relay selection strategy for delay aware image transmission in large scale multi-radio multi-channel multimedia wireless sensor network Save
- Design and Implementation of Low Power Golay Encoder Architecture Save
- Implementation of Improved High Speed SHA-256 Algorithm from RTL to GDSII Using Verilog HDL Save
- Performance and Analysis of Approximate Multipliers using Modified Dual-Stage 5:2 Compressors Save
- Low-power architectural design and implementation of reconfigurable data converters for biomedical application Save
- FPGA Implementation of Double bit Error Detection and Correction in SRAM Emulated TCAMs Save