Srinivasan Gopal

Employment

• Broadcom Ltd Irvine R & D Hardware Engineer
  2021 - Present
• Intel Corp Hillsboro Analog-Mixed Signal Design Engineer
  2018 - 2021
• Intersil Corporation Senior Design Engineer
  2010 - 2012
• PMC-Sierra Ltd Mixed Signal Design Engineer-I
  2008 - 2009

Education

• Washington State University Doctor of Philosophy
  2013 - 2018
• Indian Institute of Technology Madras Integrated BTech and MTech
  2003 - 2008

Projects & Funding

Projects & funding information is unavailable.

Publications (12)

• Highly Efficient Multiband Harmonic-Tuned GaN RF Synchronous Rectifier
  IEEE Transactions on Microwave Theory and Techniques 2023 DOI: 10.1109/TMTT.2023.3276065
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• A Reconfigurable Asynchronous SERDES for Heterogenous Chiplet Interconnects
  PROCEEDINGS OF THE SEVENTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN ISQED 2021 DOI: 10.1109/ISQED51717.2021.9424296
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• Trends and Opportunities for SRAM Based In-Memory and Near-Memory Computation
  PROCEEDINGS OF THE SEVENTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN ISQED 2021 DOI: 10.1109/ISQED51717.2021.9424263
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• A Hybrid 3D Interconnect With 2x Bandwidth Density Employing Orthogonal Simultaneous Bidirectional Signaling for 3D NoC
  IEEE Transactions on Circuits and Systems I: Regular Papers 2020 DOI: 10.1109/TCSI.2020.3013092
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• Analysis of Systematic Losses in Hybrid Envelope Tracking Modulators
  IEEE Transactions on Circuits and Systems I: Regular Papers 2019 DOI: 10.1109/TCSI.2018.2883531
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• A 25–35 GHz Neutralized Continuous Class-F CMOS Power Amplifier for 5G Mobile Communications Achieving 26% Modulation PAE at 1.5 Gb/s and 46.4% Peak PAE
  IEEE Transactions on Circuits and Systems I: Regular Papers 2019 DOI: 10.1109/tcsi.2018.2860019
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• High-Performance and Small-Form Factor Near-Field Inductive Coupling for 3-D NoC
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2018 DOI: 10.1109/TVLSI.2018.2865704
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• A 16-Gb/s Low-Power Inductorless Wideband Gain-Boosted Baseband Amplifier With Skewed Differential Topology for Wireless Network-on-Chip
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2018 DOI: 10.1109/TVLSI.2018.2856890
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• A Spatial Multi-Bit Sub-1-V Time-Domain Matrix Multiplier Interface for Approximate Computing in 65-nm CMOS
  IEEE Journal on Emerging and Selected Topics in Circuits and Systems 2018 DOI: 10.1109/jetcas.2018.2852624
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• A 28GHz 41%-PAE linear CMOS power amplifier using a transformer-based AM-PM distortion-correction technique for 5G phased arrays
  2018 IEEE International Solid - State Circuits Conference - (ISSCC) 2018 DOI: 10.1109/isscc.2018.8310356
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