Damarla Paradhasaradhi

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Publications (5)

• Design of ssaspl based shift registers with advanced leakage power reduction approaches
  International Journal of Pure and Applied Mathematics 2017
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• Implementation of low power sram cell structure at deep submicron technologies
  Journal of Theoretical and Applied Information Technology 2017
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• Study and analysis of CMOS carry look ahead adder with leakage power reduction approaches
  Indian Journal of Science and Technology 2016 DOI: 10.17485/ijst/2016/v9i17/93111
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• An advanced low complexity double error correction of an BCH decoder
  Proceeding of the IEEE International Conference on Green Computing, Communication and Electrical Engineering, ICGCCEE 2014 2014 DOI: 10.1109/ICGCCEE.2014.6922218
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• Modified wallace tree multiplier using efficient square root carry select adder
  Proceeding of the IEEE International Conference on Green Computing, Communication and Electrical Engineering, ICGCCEE 2014 2014 DOI: 10.1109/ICGCCEE.2014.6922214
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