khyamling parane

Employment

• National Institute of Technology Karnataka Research Scholar
  2015 - Present

Education

• Visvesvaraya Technological University Computer Network Engineering
  2010 - 2012

Projects & Funding

Projects & funding information is unavailable.

Publications (14)

• Hybrid Deep Learning-Based Potato and Tomato Leaf Disease Classification
  2024 DOI: 10.1007/978-981-99-9524-0_13
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• P-NoC: Performance Evaluation and Design Space Exploration of NoCs for Chip Multiprocessor Architecture Using FPGA
  Wireless Personal Communications 2020 DOI: 10.1007/s11277-020-07529-2
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• Analysis of cache behaviour and software optimizations for faster on-chip network simulations
  International Journal of System Assurance Engineering and Management 2019 DOI: 10.1007/s13198-019-00799-5
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• Design of an adaptive and reliable network on chip router architecture using FPGA
  2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019 2019 DOI: 10.1109/VLSI-DAT.2019.8741845
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• High-Performance NoCs Employing the DSP48E1 Blocks of the Xilinx FPGAs
  Proceedings - International Symposium on Quality Electronic Design, ISQED 2019 DOI: 10.1109/ISQED.2019.8697444
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• High-performance NoC simulation acceleration framework employing the xilinx DSP48E1 blocks
  2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019 2019 DOI: 10.1109/VLSI-DAT.2019.8741764
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• YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Supporting Congestion-Aware Adaptive Routing Using FPGAS
  Journal of Circuits, Systems and Computers 2019 DOI: 10.1142/S0218126619502025
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• FPGA based NoC Simulation Acceleration Framework Supporting Adaptive Routing
  2018 IEEE International Conference on Electronics, Computing and Communication Technologies, CONECCT 2018 2018 DOI: 10.1109/CONECCT.2018.8482386
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• Trace-Driven Simulation and Design Space Exploration of Network-on-Chip Topologies on FPGA
  Proceedings of the 2018 8th International Symposium on Embedded Computing and System Design, ISED 2018 2018 DOI: 10.1109/ISED.2018.8703884
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• YaNoC: Yet another network-on-chip simulation acceleration engine using FPGAS
  Proceedings of the IEEE International Conference on VLSI Design 2018 DOI: 10.1109/VLSID.2018.39
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