Piyush L. Kamani

Employment

• Government Engineering College, Bhuj Associate Professor
  2012 - Present
• Government Engineering College, Patan Assistant Professor
  2006 - 2012
• Lukhdhiraji Engineering College Lecturer
  2005 - 2006
• Sankachand Patel College of Engineering and Technology Lecturer
  2003 - 2005

Education

• Sardar Vallabhbhai National Institute of Technology Ph. D.
  2015 - Present
• Maharaja Sayajirao University of Baroda Faculty of Technology and Engineering Master of Engineering
  2001 - 2003
• Saurashtra University Bachelor of Engineering
  1995 - 1999

Projects & Funding

Projects & funding information is unavailable.

Publications (10)

• Online she technique for cascaded multilevel inverters with adjustable DC sources
  International Journal of Power and Energy Systems 2020
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• A Home-type (H-type) Cascaded Multilevel Inverter with Reduced Device Count: Analysis and Implementation
  Electric Power Components and Systems 2019 DOI: 10.1080/15325008.2019.1660735
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• Selective harmonic elimination-pulse-amplitude modulation for cascaded multilevel inverter-based STATCOM
  International Journal of Power and Energy Systems 2019 DOI: 10.2316/J.2019.203-0173
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• Univariate equation-based SHE-PWM for multilevel inverter
  Sadhana - Academy Proceedings in Engineering Sciences 2019 DOI: 10.1007/s12046-019-1095-z
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• Middle-Level SHE Pulse-Amplitude Modulation for Cascaded Multilevel Inverters
  IEEE Transactions on Industrial Electronics 2018 DOI: 10.1109/TIE.2017.2742990
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• New Selective Harmonic Elimination-Pulse-Width Modulation for Cascaded H-bridge Multilevel Inverters
  International Journal of Emerging Electric Power Systems 2018 DOI: 10.1515/IJEEPS-2018-0025
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• Simplified SHE pulse-amplitude modulation for multilevel inverters
  IET Power Electronics 2018 DOI: 10.1049/IET-PEL.2018.5538
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• Simpson's rule based SHE pulse-amplitude modulation for cascaded multilevel inverters
  International Conference on Power Systems (ICPS) 2017 DOI: 10.1109/ICPES.2017.8387361
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• A new multilevel inverter topology with reduced device count and blocking voltage
  IEEE International Conference on Environment and Electrical Engineering 2016 DOI: 10.1109/EEEIC.2016.7555722
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• A new multilevel inverter with reduced component count and reduced voltage stress
  IEEE Students' Conference on Electrical, Electronics and Computer Science (SCEECS) 2016 DOI: 10.1109/SCEECS.2016.7509312
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