Pankaj Kumar Jha

About

Pankaj Kumar Jha received his Bachelor of Science (Honors) and Masters of Science in Electronics from University of Delhi, India in 2006 and 2008 respectively . He completed his Master of Technology in VLSI Design from Malviya National Institute of Technology, Jaipur, India in 2010. He is currently working towards his Ph.D degree at Indian Institute of Technology Hyderabad, India. His research interests include the design of biomedical front-end and data converters, specially Sigma Delta modulator ADCs.

Employment

Employment history is unavailable.

Education

• Indian Institute of Technology Hyderabad PhD
  2010 - 2018
• Malaviya National Institute of Technology Jaipur M.Tech. VLSI Design
  2008 - 2010
• University of Delhi - South Campus M.Sc. Electronics
  2006 - 2008
• University of Delhi Acharya Narendra Dev College B.Sc.(Hons.)
  2003 - 2006

Projects & Funding

Projects & funding information is unavailable.

Publications (11)

• Utilizing Reference Voltage Scaling in ΣΔ ADC with Limited Input Dynamic Range Intended for Continuous Ambulatory Heartbeat Detection
  Circuits, Systems, and Signal Processing 2026 DOI: 10.1007/s00034-025-03324-1
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• A mixed-mode on-chip automatic frequency tuning technique for biopotential amplifiers
  Analog Integrated Circuits and Signal Processing 2025 DOI: 10.1007/s10470-024-02294-9
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• $$\mathbf {g_{m}/I_{D}}$$ Sizing and analysis of a recycling folded-cascode OTA for ECG signal conditioning in 0.18 $$\upmu$$m  CMOS technology
  Analog Integrated Circuits and Signal Processing 2023 DOI: 10.1007/s10470-023-02159-7
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• A Fully Analog Autonomous QRS Complex Detection and Low-Complexity Asystole, Extreme Bradycardia, and Tachycardia Classification System
  IEEE Transactions on Instrumentation and Measurement 2022 DOI: 10.1109/TIM.2022.3216392
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• Low Power Personalized ECG Based System Design Methodology for Remote Cardiac Health Monitoring
  IEEE Access 2016 DOI: 10.1109/access.2016.2629486
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• A low hardware complexity time domain quantizer for wideband multibit ΣΔ ADCs
  2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) 2015 DOI: 10.1109/primeasia.2015.7450479
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• A reconfigurable medically cohesive biomedical front-end with ΣΔ ADC in 0.18µm CMOS
  2015 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC) 2015 DOI: 10.1109/embc.2015.7318491
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• A 2μW biomedical frontend with ΣΔ ADC for self-powered U-healthcare devices in 0.18μm CMOS technology
  2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS) 2015 DOI: 10.1109/newcas.2015.7182054
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• An enhanced recycling folded cascade OTA with a positive feedback
  2013 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) 2013 DOI: 10.1109/primeasia.2013.6731196
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• Modeling a IF double sampling bandpass switched capacitor ΣΔ ADC with a symmetric noise transfer function for WiMAX/WLAN
  2012 5th International Conference on Computers and Devices for Communication (CODEC) 2012 DOI: 10.1109/codec.2012.6509222
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