DV
Dr. Telajala Venkata Mahendra
VIT-AP University, National Institute of Technology Meghalaya
Employment
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VIT-AP University Assistant Professor2020 - Present
Education
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National Institute of Technology Meghalaya PhD2017 - 2021
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National Institute of Technology Meghalaya M.Tech/VLSI Design2014 - 2016
Projects & Funding
Projects & funding information is unavailable.
Publications (20)
- Match-line control unit for power and delay reduction in hybrid CAM Save
- A novel low-power matchline evaluation technique for content addressable memory (CAM) Save
- Energy-Efficient Precharge-Free Ternary Content Addressable Memory (TCAM) for High Search Rate Applications Save
- Low-power content addressable memory design using two-layer P-N match-line control and sensing Save
- Pseudo-Static Master-Slave Match-Line Scheme for Sustainable-Performance and Energy-Efficient Content Addressable Memory Save
- The analogy of matchline sensing techniques for content addressable memory (CAM) Save
- Low Match-Line Voltage Swing Technique for Content Addressable Memory Save
- Performance analysis of N-CAM, P-CAM and TG-CAM Using 45-nm technology Save
- Low discharge precharge free matchline structure for energy-efficient search using CAM Save
- Efficient Matchline Controller for Hybrid Content Addressable Memory Save