Manoranjan Pradhan

Employment

• Veer Surendra Sai University of Technology Associate Professor
  2001 - Present

Education

• Veer Surendra Sai University of Technology Phd
• VSS University of Technology ME
• Veer Surendra Sai University of Technology BE

Projects & Funding

Projects & funding information is unavailable.

Publications (33)

• Signed multiplication architecture using Vedic Urdhva Tiryagbhyam algorithm
  Facta universitatis - series: Electronics and Energetics 2026 DOI: 10.2298/FUEE2601137K
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• Design and Analysis of Area and Time Efficient Signed Square Architecture Using Nonconventional Method
  Journal of Circuits, Systems and Computers 2025 DOI: 10.1142/S0218126625501233
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• Occurrence of Nonlinear Electron Mobility in GaAs/InxGa1−xAs Coupled Double Quantum Well FET
  2024 DOI: 10.1007/978-981-99-4495-8_7
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• Intersubband effects on electron mobility in GaAs/InxGa1-xAs Quantum well FET with asymmetric doping profiles
  Proceedings of 5th International Conference on 2023 Devices for Integrated Circuit, DevIC 2023 2023 DOI: 10.1109/DevIC57758.2023.10134919
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• Analysis of Combinational Delay in Signed Binary Multiplier
  Proceedings of the 2022 International Conference on Connected Systems and Intelligence, CSI 2022 2022 DOI: 10.1109/CSI54720.2022.9924000
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• Comparative Analysis of Decimal Fixed-Point Parallel Multipliers Using Signed Digit Radix-4, 5 and 10 Encodings
  Lecture Notes in Electrical Engineering 2022 DOI: 10.1007/978-981-16-2761-3_32
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• Structural Asymmetry related Nonlinear Mobility of Electron in InxGa1-xAs/GaAs Quantum well FET
  Proceedings of 2022 IEEE International Conference of Electron Devices Society Kolkata Chapter, EDKCON 2022 2022 DOI: 10.1109/EDKCON56221.2022.10032871
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• Study of nonmonotonic electron mobility due to influence of asymmetric structure parameters in pseudomorphic heterojunction field effect transistors
  Physica Scripta 2022 DOI: 10.1088/1402-4896/ac9862
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• Improved Redundant Binary Adder Realization in FPGA
  Journal of Circuits, Systems and Computers 2021 DOI: 10.1142/S021812662150287X
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• A Time Efficient Redundant Binary Adder with Modified Encoding Bits
  2021 International Conference on Nascent Technologies in Engineering, ICNET 2021 - Proceedings 2021 DOI: 10.1109/ICNTE51185.2021.9487700
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