Daniel Valencia

Employment

• San Diego State University Post-Doctoral Researcher

Education

• San Diego State University Ph.D.
  2019 - 2024
• San Diego State University M.S
  2017 - 2019

Projects & Funding

Projects & funding information is unavailable.

Publications (15)

• An Efficient Brain-Switch for Asynchronous Brain-Computer Interfaces
  IEEE Transactions on Biomedical Circuits and Systems 2025 DOI: 10.1109/TBCAS.2024.3396115
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• Efficient in Vivo Neural Signal Compression Using an Autoencoder-Based Neural Network
  IEEE Transactions on Biomedical Circuits and Systems 2024 DOI: 10.1109/TBCAS.2024.3359994
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• A generalized hardware architecture for real-time spiking neural networks
  Neural Computing and Applications 2023 DOI: 10.1007/s00521-023-08650-6
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• Partially binarized neural networks for efficient spike sorting
  Biomedical Engineering Letters 2023 DOI: 10.1007/s13534-022-00255-7
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• Power-efficient in vivo brain-machine interfaces via brain-state estimation
  Journal of Neural Engineering 2023 DOI: 10.1088/1741-2552/acb385
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• In vivo neural spike detection with adaptive noise estimation
  Journal of Neural Engineering 2022 DOI: 10.1088/1741-2552/ac8077
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• Towards in vivo neural decoding
  Biomedical Engineering Letters 2022 DOI: 10.1007/s13534-022-00217-z
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• Neural Spike Sorting Using Binarized Neural Networks
  IEEE Transactions on Neural Systems and Rehabilitation Engineering 2021 DOI: 10.1109/TNSRE.2020.3043403
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• An Artificial Neural Network Processor With a Custom Instruction Set Architecture for Embedded Applications
  IEEE Transactions on Circuits and Systems I: Regular Papers 2020 DOI: 10.1109/TCSI.2020.3003769
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• A Real-Time Spike Sorting System Using Parallel OSort Clustering
  IEEE Transactions on Biomedical Circuits and Systems 2019 DOI: 10.1109/TBCAS.2019.2947618
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• Frameworks for Efficient Brain-Computer Interfacing
  IEEE Transactions on Biomedical Circuits and Systems 2019 DOI: 10.1109/TBCAS.2019.2947130
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• An Efficient Hardware Architecture for Template Matching-Based Spike Sorting
  IEEE Transactions on Biomedical Circuits and Systems 2019 DOI: 10.1109/tbcas.2019.2907882
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• Compact ang High-throughput Parameterizable Architectures for Memory-based FFT Algorithms
  IET Circuits, Devices & Systems 2019 DOI: 10.1049/iet-cds.2018.5556
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• High-throughput and compact reconfigurable architectures for recursive filters
  IET Communications 2018 DOI: 10.1049/iet-com.2018.0085
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• High-throughput and compact FFT architectures using the Good–Thomas and Winograd algorithms
  IET Communications 2018 DOI: 10.1049/iet-com.2017.0837
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