Deepika Gupta

About

I received the B.E. degree in Electronics & Communication Engineering from the University of Rajasthan, Rajasthan (India) in 2009, M.Tech. degree in Very Large Scale Integration (VLSI) design from Dr B R Ambedkar National Institute of Technology, Jalandhar (India) in 2013 and Ph.D. degree in Electrical Engineering from Indian Institute of Technology, Indore (India) in 2017. My research interests include simulation and modelling of 3-D charge trap (CT) NAND flash memory devices, Novel semiconductor devices and Advanced non volatile memories.. Also, I have received gold medal during M.Tech at NIT jalandhar and “GARGI AWARD” from Govt. of Rajasthan during HSC for academic performance.

Employment

• International Institute of Information Technology Assistant Professor
  2019 - Present
• Veer Surendra Sai University of Technology Assistant Professor
  2018 - Present
• Rajasthan Technical University Assistant Professor
  2018 - 2018
• Mewar University Assistant Professor
  2013 - 2013
• Modern Institute of Technology and Research Centre Lecturer
  2010 - 2011

Education

• Indian Institute of Technology Indore Ph.D.
  2014 - 2017
• Dr. B. R. Ambedkar National Institute of Technology Jalandhar M.Tech
  2011 - 2013

Projects & Funding

Projects & funding information is unavailable.

Publications (16)

• A cascaded nonlinear VGSOT-MTJ-based arbiter architecture for variation-aware VLSI design
  Integration 2026 DOI: 10.1016/j.vlsi.2026.102811
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• Device–circuit co-design of field-free VGSOT-MTJ for a delay-tunable energy-efficient arbiter PUF
  Journal of Magnetism and Magnetic Materials 2026 DOI: 10.1016/j.jmmm.2026.174385
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• Energy-Efficient and Attacks Resilient PUF Design Exploiting VGSOT-MTJ
  IEEE Open Journal of Nanotechnology 2025 DOI: 10.1109/OJNANO.2025.3625466
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• Electrical Modeling and Performance Analysis of Cu and CNT Based TSV-Bump-RDL
  IEEE Transactions on Nanotechnology 2024 DOI: 10.1109/TNANO.2024.3408310
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• High-Frequency Electromagnetic Eddy Effect Modeling for Cylindrical and Tapered Bump
  IEEE Transactions on Electromagnetic Compatibility 2023 DOI: 10.1109/TEMC.2023.3307816
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• Improvement of memory performance of 3-D NAND flash memory with retrograde channel doping
  Memories - Materials, Devices, Circuits and Systems 2023 DOI: 10.1016/j.memori.2023.100031
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• Effect of Spacer Dielectric on the Program Disturb of 3-D Junction-Free NAND Flash Memory
  Journal of Nanoelectronics and Optoelectronics 2019
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• Improvement of short channel performance of junction-free charge trapping 3D NAND flash memory
  IET Micro and Nano Letters 2017 DOI: 10.1049/mnl.2016.0641
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• Investigation of Band-Gap Engineered Silicon-Oxide-Nitride-Oxide-Silicon Flash Memory with High-k Dielectrics in Tunnel Barrier and Its Impact on Charge Retention Dynamics
  Journal of Nanoelectronics and Optoelectronics 2016
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• Impact of LDD Depth Variations on the Performance Characteristics of SONOS NAND Flash Device
  IEEE transaction on Device and Material Reliability 2016
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