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Publications (12)
- Interface trap dynamics and thermal effects in novel junctionless dual gate inverted-U-shaped FinFETs for sub-5 nm node: device to circuit level implementation Save
- Impact of interface traps and noise analysis on dual material graded channel CGAA FET: A device reliability Save
- Interface Trap Characterization in Junctionless Forksheet FET at Sub-3 nm Technology Node: A Reliability Assessment on Digital, Analog/RF, and Circuit Applications Save
- Optimization of Sidewall Spacer Engineering at Sub-5 nm Technology Node For JL-Nanowire FET: Digital/Analog/RF/Circuit Perspective Save
- Spacer Design Strategies at sub-5 nm technology node for Junctionless Forksheet FET: Bridging Device Optimization and Circuit Efficacy - A Dielectric Perspective Save
- An analytical drain current modelling of DMGC CGAA FET: A circuit level implementation Save
- Analytical modeling of a dual-material graded-channel cylindrical gate-all-around FET to minimize the short-channel effects Save
- Circuit Level Analysis of a Dual Material Graded Channel (DMGC) Cylindrical Gate All Around (CGAA) FET at Nanoscale Regime Save
- Design Considerations into Circuit Applications for Structurally Optimised FinFET Save
- Optimization of DMGC CGAA FET Under Heavy Ion Irradiation Environment: A Reliability Analysis Save