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Manu Bansal

Thapar Institute of Engineering and Technology (Deemed to be University), Thapar University

ORCID iD 0000-0003-4654-7127
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Dr. Manu Bansal – ORCID Biography (5000 characters)
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Dr. Manu Bansal is Associate Professor in the Department of Electronics and Communication Engineering (ECED) at Thapar Institute of Engineering & Technology (TIET), Patiala, Punjab, India. With 27 years of exemplary service since February 1998, she has established herself as a leading researcher and educator in VLSI design, reconfigurable hardware, lightweight cryptography, and embedded security systems.
She earned her B.E. (1997), M.E. (2003), and Ph.D. (2018) from TIET. Her doctoral thesis, “Study and Analysis of Minimization Algorithms for VLSI Circuit Synthesis,” pioneered evolutionary-algorithm-driven Binary Decision Diagram (BDD) optimization, achieving up to 38% reduction in node count for benchmark circuits. This work laid the foundation for her subsequent contributions in low-power FPGA designs and hardware-security co-design.
Dr. Bansal’s research portfolio spans VLSI design automation, FPGA-based accelerators, lightweight cryptography for IoT, steganography, VANET security, and wireless sensor networks. Her seminal reviews — “A Review on Lightweight Cryptography Algorithms for Data Security and Authentication in IoTs” (156+ citations) and “A Review on VANET Security Attacks and Their Countermeasure” (80+ citations) — are widely referenced. She has authored 40+ publications in SCI/Scopus journals (IEEE TVLSI, Microprocessors & Microsystems, JRTIP) and IEEE/ACM conferences, with key contributions in genetic-algorithm-based BDD minimization, secure hardware trojan detection, FPGA-accelerated depth cameras, and real-time image processing for search-and-rescue drones.
As Co-Principal Investigator of the ₹166 Lakh MeitY-sponsored “SMDP-Chips to System Design” project (2015–2021), she established advanced VLSI and FPGA laboratories, trained 220+ faculty members across India, and mentored industry-relevant projects with Cadence, Synopsys, and Xilinx tools. She also contributed to the DoE-funded Special Manpower Development Programme for VLSI (Phase-I, 1998–2005).
Dr. Bansal has guided 52 M.Tech./M.E. theses, with alumni placed at Intel, Qualcomm, STMicroelectronics, and Texas Instruments. Her students have won Best Paper awards at IEEE conferences and filed three Indian patents on FPGA-based secure steganography and drone vision systems.
Her administrative leadership is extensive: BE-ECE Program Coordinator (2014–2023), Internship Coordinator (ECED, 2015–2023), Laboratory In-charge of “VLSI Chips to Systems” Lab (2015–present) and Digital Electronics Lab (2005–2008). She served on TIET’s Board of Governors (2021–2022), Senate, Staff Affairs Committee, and chaired multiple accreditation teams for NBA/NAAC, ensuring A++ grade outcomes.
A Life Member of ISTE, IETE, Metrology Society of India, and member of VLSI Society of India, Dr. Bansal has twice received TIET’s Performance Incentive Scheme award. Her current projects focus on FPGA-accelerated depth cameras using ToF sensors, secure edge computing for autonomous SAR drones, and lightweight cryptographic primitives for resource-constrained environments.
Dr. Bansal continues to bridge academia and industry, fostering innovations that enhance real-time performance and security in mission-critical embedded systems.

Employment

  • Thapar Institute of Engineering and Technology (Deemed to be University) Associate Professor
    1998 - Present

Education

  • Thapar University BE(EC), ME(EC)
    2003 - Present

Projects & Funding

Projects & funding information is unavailable.

Publications (11)