Pramod Udupa

Employment

• Samsung (India) Staff Engineer/Researcher
  2018 - Present
• Intel (India) IP Logic Design Engineer
  2016 - 2018
• Signalchip Innovations Private Limited Design Engineer
  2014 - 2016

Education

Education history is unavailable.

Projects & Funding

Projects & funding information is unavailable.

Publications (8)

• SABRE: A Compression-Aware BF16 Accelerator for Neuromorphic Attention
  Kunal Kishore, Manish Nagaraju, Anshul Raghavendra Katti +4 more
  2026 DOI: 10.1145/3801487.3801814
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• Accelerating Depthwise Convolution and Pooling Operations on z-First Storage CNN Architectures
  Pramod Udupa, Gopinath Mahale, Kiran Kolar Chandrasekharan

  +1 more

  • Sehwan Lee
  2020 IEEE International Symposium on Circuits and Systems (ISCAS) 2020 DOI: 10.1109/iscas45731.2020.9180863
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• IKW: Inter-Kernel Weights for Power Efficient Edge Computing
  Pramod Udupa, Gopinath Mahale, Kiran Kolar Chandrasekharan

  +1 more

  • Sehwan Lee
  IEEE Access 2020 DOI: 10.1109/access.2020.2993506
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• WinDConv: A Fused Datapath CNN Accelerator for Power-efficient Edge Devices
  Gopinath Mahale, Pramod Udupa, Kiran Kolar Chandrasekharan

  +1 more

  • Sehwan Lee
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2020 DOI: 10.1109/tcad.2020.3013096
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• A block-parallel architecture for initial and fine synchronization in OFDM systems
  Pramod Udupa, Olivier Sentieys, Pascal Scalart
  2013 IEEE International Conference on Communications (ICC) 2013 DOI: 10.1109/icc.2013.6655326
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• A Novel Hierarchical Low Complexity Synchronization Method for OFDM Systems
  Pramod Udupa, Olivier Sentieys, Pascal Scalart
  2013 IEEE 77th Vehicular Technology Conference (VTC Spring) 2013 DOI: 10.1109/vtcspring.2013.6691838
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• A hardware accelerated system for deep packet inspection
  Adarsha Rao, Pramod Udupa
  Eighth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010) 2010 DOI: 10.1109/memcod.2010.5558646
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• Accelerating Numerical Linear Algebra Kernels on a Scalable Run Time Reconfigurable Platform
  Prasenjit Biswas, Pramod Udupa, Rajdeep Mondal

  +4 more

  • Keshavan Varadarajan
  • Mythri Alle
  • S. K. Nandy
  • Ranjani Narayan
  2010 IEEE Computer Society Annual Symposium on VLSI 2010 DOI: 10.1109/isvlsi.2010.65
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