Raj Kumar Gajavelly

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Publications (11)

• LISA: LLM Informed Systemverilog Assertion generation with RAG and Chain-of-Thought
  2025 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2025 DOI: 10.1109/isvlsi65124.2025.11130226
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• New Branching Heuristics for Incremental Bounded Model Checking
  2025 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2025 DOI: 10.1109/isvlsi65124.2025.11130348
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• BMC Engine Sequencing with Graph Neural Network Embeddings of Hardware Circuits
  2025 38th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID) 2025 DOI: 10.1109/vlsid64188.2025.00041
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• Toward Exhaustive Sequential Redundancy Removal
  Formal Methods in Computer-Aided Design 2024 DOI: 10.34727/2024/ISBN.978-3-85448-065-5_27
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• MAB-BMC: A Formal Verification Enhancer by Harnessing Multiple BMC Engines Together
  ACM Transactions on Design Automation of Electronic Systems 2024 DOI: 10.1145/3675168
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• Harnessing Multiple BMC Engines together for Efficient Formal Verification
  2023 DOI: 10.1145/3610579.3611083
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• Input Elimination Transformations for Scalable Verification and Trace Reconstruction
  2019 Formal Methods in Computer Aided Design (FMCAD) 2019 DOI: 10.23919/fmcad.2019.8894294
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• Symbolic trajectory evaluation for word-level verification: theory and implementation
  Formal Methods in System Design 2017 DOI: 10.1007/s10703-017-0268-9
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• The art of semi-formal bug hunting
  Proceedings of the 35th International Conference on Computer-Aided Design 2016 DOI: 10.1145/2966986.2967079
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• Word-Level Symbolic Trajectory Evaluation
  Computer Aided Verification 2015 DOI: 10.1007/978-3-319-21668-3_8
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