Abhishek Yadav

About

I am a researcher specializing in hardware accelerators, hardware/software co-design, and edge AI applications. My work focuses on designing efficient hardware architectures for edge AI by optimizing throughput, latency, power, and security.

I work with FPGAs (ZCU104, PYNQ-Z2), Google TPU, AMD-Xilinx DPU accelerators, and ASIC (GPDK-90nm), exploring techniques like quantization, buffer tiling, fusion, and zero-skipping to enhance neural network performance. Proficient in C++, Python, and Verilog, I bring strong expertise in machine learning algorithms and system optimization.
Below are the URLs of my Website, GitHub, Medium, and Google Scholar repositories:
https://abhiiishekyadav.abhiiishekyadav.workers.dev
https://github.com/Abhiiishekyadav
https://medium.com/@abhiiishekyadav
https://shorturl.at/7CZWS

I am passionate about driving innovation at the intersection of AI and hardware.

Employment

• Synopsys Pvt Ltd Former Post graduate Trainee in
  2020 - 2021
• Qualcomm Pvt Ltd Former Interim Engineering Intern
  2020 - 2020
• SUTD Senior Research Assistant
• Indian Institute of Technology Jodhpur Research Scholar

Education

• IIIT ALLAHABAD M.Tech
  2018 - 2020
• FGIET RAEBARELI B.Tech
  2012 - 2016

Projects & Funding

Projects & funding information is unavailable.

Publications (23)

• A Graph-Based Methodology for Dynamic KV-Cache Compression in Transformer Inference
  2026 IEEE International Symposium on Circuits and Systems (ISCAS) 2026 DOI: 10.1109/iscas66217.2026.11562780
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• Zero-Shot Fused Attention-Based GPT-2 Accelerator for Resource-Constrained Embedded Platform
  IEEE Embedded Systems Letters 2026 DOI: 10.1109/LES.2025.3583743
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• FPGA-Based Medical Image Processing Using Hardware-Software Co-Design Approach
  IEEE Transactions on Biomedical Circuits and Systems 2026 DOI: 10.1109/TBCAS.2025.3594840
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• Hardware acceleration of DL-based computer vision tasks targeting reconfigurable platforms
  The Journal of Supercomputing 2026 DOI: 10.1007/s11227-026-08713-0
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• On-Chip Implementation of Neural Network-Based Classifier Models for E-Nose With Chemometric Analysis
  IEEE Transactions on Instrumentation and Measurement 2025 DOI: 10.1109/TIM.2025.3554292
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• Lightweight Surveillance Image Classification Through Hardware-Software Co-Design
  IEEE Embedded Systems Letters 2025 DOI: 10.1109/LES.2025.3534237
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• Multi-Object Detection Through Meta-Training in Resource-Constrained UAV-Based Surveillance Applications
  2025 38th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID) 2025 DOI: 10.1109/vlsid64188.2025.00061
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• Resource-Efficient LSTM Architecture for Keyword Spotting with CORDIC-Activation Approximation
  2025 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2025 DOI: 10.1109/isvlsi65124.2025.11130307
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• Hierarchical Multiscale CNN With Frequency-Aware Attention for Enhanced HAR
  IEEE Sensors Journal 2025 DOI: 10.1109/JSEN.2025.3586069
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• Highly Sensitive Gas Sensor-based on Zn 2 SnO 4 Nanocomposite for Biomarker Detection
  2025 6th International Conference on Electronics and Sustainable Communication Systems (ICESC) 2025 DOI: 10.1109/icesc65114.2025.11212380
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