Bheemudu Vadthya

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Publications (4)

• Device and circuit level investigation of interface trap charge effects on the transport and noise characteristics of JL-NSFETS at sub-5 nm nodes
  Physica Scripta 2026 DOI: 10.1088/1402-4896/ae8b36
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• Spacer Design Strategies at Sub-5-nm Technology Node for Junctionless Forksheet FET: Bridging Device Optimization and Circuit Efficacy—A Dielectric Perspective
  IEEE Transactions on Dielectrics and Electrical Insulation 2025 DOI: 10.1109/TDEI.2024.3497877
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• Interface Trap Characterization in Junctionless Forksheet FET at Sub-3 nm Technology Node: A Reliability Assessment on Digital, Analog/RF, and Circuit Applications
  IEEE Transactions on Device and Materials Reliability 2025 DOI: 10.1109/TDMR.2024.3516084
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• Device to circuit level implementation of JL-NSFET for DC/analog/RF applications at sub-5nm technology node: design optimization and temperature analysis
  Physica Scripta 2024 DOI: 10.1088/1402-4896/ad896c
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